Datasheet

21
LTC2400
pin on each falling edge of SCK. The internally generated
serial clock is output to the SCK pin. This signal may be
used to shift the conversion result into external circuitry.
After the 32nd rising edge, CS is pulled HIGH and a new
conversion is immediately started. This is useful in appli-
cations requiring periodic monitoring and ultralow power.
Figure 14 shows the average supply current as a function
of capacitance on CS.
It should be noticed that the external capacitor discharge
current is kept very small in order to decrease the con-
verter power dissipation in the sleep state. In the autostart
mode the analog voltage on the CS pin cannot be observed
without disturbing the converter operation using a regular
oscilloscope probe. When using this configuration, it is
important to minimize the external leakage current at the
CS pin by using a low leakage external capacitor and
properly cleaning the PCB surface.
The internal serial clock mode is selected every time the
voltage on the CS pin crosses an internal threshold volt-
age. An internal weak pull-up at the SCK pin is active while
CS is discharging; therefore, the internal serial clock
timing mode is automatically selected if SCK is floating. It
is important to ensure there are no external drivers pulling
SCK LOW while CS is discharging.
DIGITAL SIGNAL LEVELS
The LTC2400’s digital interface is easy to use. Its digital
inputs (F
O
, CS and SCK in External SCK mode of operation)
accept standard TTL/CMOS logic levels and the internal
hysteresis receivers can tolerate edge rates as slow as
100µs. However, some considerations are required to take
advantage of exceptional accuracy and low supply current.
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
In order to preserve the LTC2400’s accuracy, it is very
important to minimize the ground path impedance which
may appear in series with the input and/or reference signal
and to reduce the current which may flow through this
path. The GND pin should be connected to a low resistance
ground plane through a minimum length trace. The use of
multiple via holes is recommended to further reduce the
APPLICATIONS INFORMATION
WUU
U
CAPACITANCE ON CS (pF)
1
5
6
7
1000 10000
2400 F12
4
3
10 100 100000
2
1
0
t
SAMPLE
(SEC)
V
CC
= 5V
V
CC
= 3V
Figure 12. CS Capacitance vs t
SAMPLE
CAPACITANCE ON CS (pF)
0
SAMPLE RATE (Hz)
3
4
5
1000
100000
2400 F13
2
1
0
10 100 10000
6
7
8
V
CC
= 5V
V
CC
= 3V
Figure 13. CS Capacitance vs Output Rate
CAPACITANCE ON CS (pF)
1
0
SUPPLY CURRENT (µA
RMS
)
50
100
150
200
250
300
10 100 1000 10000
2400 F14
100000
V
CC
= 5V
V
CC
= 3V
Figure 14. CS Capacitance vs Supply Current