Datasheet

LTC2414/LTC2418
20
241418fa
The serial clock mode is selected on the falling edge of CS.
To select the external serial clock mode, the serial clock pin
(SCK) must be LOW during each CS falling edge.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0 if
the device is in the sleep state. Independent of CS, the
device automatically enters the low power sleep state once
the conversion is complete.
When the device is in the sleep state, its conversion result
is held in an internal static shift register. The device
remains in the sleep state until the first rising edge of SCK
is seen while CS is LOW. The input data is then shifted in
via the SDI pin on the rising edge of SCK (including the
first rising edge) and the output data is shifted out of the
SDO pin on each falling edge of SCK
. This enables
external circuitry to latch the output on the rising edge of
SCK. EOC can be latched on the first rising edge of SCK
and the last bit of the conversion result can be latched on
the 32nd rising edge of SCK. On the 32nd falling edge of
SCK, the device begins a new conversion. SDO goes HIGH
(EOC = 1) indicating a conversion is in progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first rising edge and the 32nd
falling edge of SCK, see Figure 6. On the rising edge of CS,
the device aborts the data output state and immediately
initiates a new conversion. If the device has not finished
loading the last input bit A0 of SDI by the time CS is pulled
HIGH, the address information is discarded and the previ-
ous address is kept. This is useful for systems not requir-
ing all 32 bits of output data, aborting an invalid conversion
cycle or synchronizing the start of a conversion.
Figure 6. External Serial Clock, Reduced Data Output Length
APPLICATIO S I FOR ATIO
WUUU
(1) (0) EN SGL A2 A1 A0
ODD/
SIGN
SDI
DON’T CARE DON’T CARE
SDO
SCK
(EXTERNAL)
CS
DATA
OUTPUT
CONVERSIONSLEEP
SLEEP
SLEEP
TEST EOC
DATA OUTPUT
Hi-Z Hi-ZHi-Z
CONVERSION
241418 F06
MSBSIG
BIT 8BIT 27 BIT 26 BIT 25 BIT 24 BIT 9BIT 28BIT 29BIT 30
EOC
BIT 31BIT 0
EOC
Hi-Z
TEST EOC
V
CC
F
O
REF
+
REF
–
CH0
CH7
CH8
CH15
COM
SCK
SDI
SDO
CS
GND
919
11
12
21
28
1
8
10
18
17
15
16
20
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUTS
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
CC
1µF
2.7V TO 5.5V
LTC2414/
LTC2418
4-WIRE
SPI INTERFACE
•
•
•
•
•
•
•
•
•
•
•
•
TEST EOC
(OPTIONAL)