Datasheet

LTC2440
24
2440fd
APPLICATIONS INFORMATION
fastest expected input signal. Figure 20 shows the large
signal response of the circuit in Figure 19.
3. Measure noise performance of the complete circuit. A
good technique is to build one amplifi er for each input,
even if only one will be used in the end application. Bias
both amplifi er outputs to midscale, with the inputs tied
together. Verify that the noise is as expected, taking into
account the bandwidth of the LTC2440 inputs for the OSR
being used, the amplifi er’s broadband voltage noise and
1/f corner (if any) and any additional noise due to the
amplifi er’s current noise and source resistance.
For more information on testing high linearity ADCs, refer
to Linear Technology Design Solutions 11.
Input Bandwidth and Frequency Rejection
The combined effect of the internal SINC
4
digital fi lter and
the digital and analog autocalibration circuits determines
the LTC2440 input bandwidth and rejection characteristics.
The digital fi lter’s response can be adjusted by setting the
oversample ratio (OSR) through the SPI interface or by
supplying an external conversion clock to the f
O
pin.
Figure 19. Buffering the LTC2440 from High Impedance Sources Using a Chopper Amplifi er
Figure 20. Large Signal Input Settling Time Indicates
Completed Settling with Selected Load Capacitance.
Figure 21. Dynamic Input Current is Attenuated by Load
Capacitance and Completely Settled Before the Next Conversion
Sample Resulting in No Reduction in Performance.
V
CC
f
O
REF
+
REF
–
SCK
BUSY
IN
+
IN
–
SDO
CS
EXT
0.1μF
4
13
5
6
12
1, 8, 9, 16
11
10
15
SDI
7
5V
10μF0.01μF
LTC2440
2440 F19
14
10Ω
IN+
5k
C2
C2, C5 TAIYO YUDEN JMK107BJ105MA
4.7μF
8-12V
LT1236-5
1μF
C1
R1
R2
R4
R5
0.01μF
1
/
2
LTC2051HV
C5
1μF
10Ω
IN–
5k
C4
0.01μF
1
/
2
LTC2051HV
+
–
+
–
2440 F20
100μs/DIV
100mV/DIV
2440 F21
5ns/DIV
2mV/DIV