Datasheet

14
LTC1923
1923f
pulled to V
DD
forcing the gate of M2 low, which allows the
bridge to operate as described earlier. When a fault occurs
and FAULT is asserted low, M1 is shut off, forcing the gate
of M2 high, shutting that device off. The power path is thus
opened, ensuring no current is delivered to the TEC. M2
wants to have low R
DS(ON)
(less than the value of R
S
to
minimize the power losses associated with it). R
P1
and
R
P2
can be selected on the order of 100k.
The lower comparator threshold level is 20% (twenty
percent) of V
SET
and the upper comparator threshold level
is 350mV below V
SET
, where V
SET
is the voltage applied on
the V
SET
pin. V
SET
is typically tied to the bias source for the
thermistor divider so that any variations will track out.
The V
SET
pin has a high input impedance so that a divided-
down voltage can be supplied to this pin to modify the
acceptable thermistor impedance range. This is shown in
Figure 6. The voltage applied to the V
SET
pin must be a
minimum of 2V. The lower thermistor impedance thresh-
old is:
R
RR
RR
TH LOWER()
.• •
.•
=
+
02 1 3
208 3
The upper impedance threshold is:
R
RR R R
RRR
TH UPPER()
–( )
()
=
+
()
++
13 2 3
223
α
α
where α = 0.35/V
SET
.
Changing R1 also changes the valid thermistor impedance
range.
Example: V
REF
= V
SET
= 2.5V
R1 = 10k, R2 = 0Ω, R3 = open
R
TH
= 10k NTC thermistor with a temperature coeffi-
cient of –4.4%/C at 25°C.
The acceptable thermistor impedance range before caus-
ing a fault is 2.5kΩ to 61kΩ. This corresponds to a valid
temperature range of between about –10°C and 60°C.
To ensure the part does not power up with a latched fault
at start-up, a fault will not be latched until soft-start has
completed. This corresponds to the voltage on SS reach-
ing 1.5V. For a 1µF soft-start capacitor, this delay is
approximately 1 second. This provides enough time for all
supplies (V
DD
, setpoint reference and V
REF
) to settle at
their final values.
TEC Voltage Clamping
An internal clamp circuit is included to protect the TEC
from an overvoltage condition. When the differential volt-
age across the TEC exceeds 2.5V, the error amplifier
output voltage at the input of the PWM comparator is
limited. This clamps the duty cycle of the output drivers,
and therefore, the voltage across the TEC. The voltage
where clamping occurs can be increased by placing a
resistor divider in parallel with the TEC and by making the
appropriate connections to TEC
+
and TEC
–
as shown in
Figure 7. The divider increases the voltage across the TEC,
V
TECOOLER
, where the clamp activates, to:
V
R
R
R
k
V
R
k
R
k
TECOOLER
TE
TE
TE
CM
TE
TE
=
++












+
1
100
25
200
1
200
1
2
11
1
•.–
V
REF
V
SET
V
THRM
1923 F06
R2
R1
R
TH
10k
NTC
R3
Figure 6. Modifying the Acceptable Thermistor Range
TEC
TEC
+
R
TE2
R
TE1
1923 F07
V
TECOOLER
V
CM
+–
TEC
–
Figure 7. Increasing Voltage Clamp Threshold
OPERATIO
U