Datasheet

LTC4228-1/LTC4228-2
4
422812f
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
IN
= 12V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
∆V
HGATE(PG)
Gate-Source Voltage for Power Good
l
3.6 4.2 4.8 V
I
HGATE(UP)
External N-Channel Gate Pull-Up Current Gate Drive On, HGATE = 0V
l
–7 –10 –13 µA
I
HGATE(DN)
External N-Channel Gate Pull-Down Current Gate Drive Off, OUT = 12V,
HGATE = OUT + 5V
l
150 300 500 µA
I
HGATE(FPD)
External N-Channel Gate Fast
Pull-Down Current
Fast Turn-Off, OUT = 12V,
HGATE = OUT + 5V
l
100 200 300 mA
t
PHL(SENSE)
Sense Voltage (SENSEn
+
– SENSEn
–
)
High to HGATEn Low
∆V
SENSE
= 300mV, C
HGATE
= 10nF
l
0.5 1 µs
t
OFF(HGATE)
ENn High to HGATEn Low
ONn Low to HGATEn Low
SENSEn
+
Low to HGATEn Low
l
l
l
20
10
10
40
20
20
µs
µs
µs
t
D(HGATE)
ONn High, ENn Low to HGATEn
Turn-On Delay
l
50 100 150 ms
t
P(HGATE)
ONn to HGATEn Propagation Delay ON = Step 0.8V to 2V
l
10 20 µs
Input/Output Pin
V
ON(TH)
ONn Threshold Voltage ON Rising
l
1.21 1.235 1.26 V
∆V
ON(HYST)
ONn Hysteresis
l
40 80 140 mV
V
ON(RESET)
ONn Fault Reset Threshold Voltage ON Falling
l
0.55 0.6 0.63 V
I
ON(LEAK)
ONn Input Leakage Current ON = 5V
l
0 ±1 µA
V
EN(TH)
ENn Threshold Voltage EN Rising
l
1.185 1.235 1.284 V
∆V
EN(HYST)
ENn Hysteresis
l
40 130 200 mV
I
EN(UP)
ENn Pull-Up Current EN = 1V
l
–7 –10 –13 µA
V
TMR(TH)
TMRn Threshold Voltage TMR Rising
TMR Falling
l
l
1.198
0.15
1.235
0.2
1.272
0.25
V
V
I
TMR(UP)
TMRn Pull-Up Current TMR = 1V, In Fault Mode
l
–75 –100 –125 µA
I
TMR(DN)
TMRn Pull-Down Current TMR = 2V, No Faults
l
1.4 2 2.6 µA
I
TMR(RATIO)
TMRn Current Ratio I
TMR(DN)
/I
TMR(UP)
l
1.4 2 2.7 %
I
OUT
OUTn Current OUT = 11V, IN = 12V, ON = 2V
OUT = 13V, IN = 12V, ON = 2V
l
l
50
2.5
120
5
µA
mA
V
OL
Output Low Voltage
(FAULTn, PWRGDn, STATUSn)
I = 1mA
l
0.15 0.4 V
V
OH
Output High Voltage
(FAULTn, PWRGDn, STATUSn)
I = –1µA
l
INTV
CC
– 1 INTV
CC
– 0.5 V
I
OH
Input Leakage Current
(FAULTn, PWRGDn, STATUSn)
V = 18V
l
0 ±1 µA
I
PU
Output Pull-Up Current
(FAULTn, PWRGDn, STATUSn)
V = 1.5V
l
–7 –10 –13 µA
t
RST(ON)
ONn Low to FAULTn High
l
20 40 µs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to GND unless otherwise
specified.
Note 3: An internal clamp limits the DGATE and CPO pins to a minimum of
10V above and a diode below IN. Driving these pins to voltages beyond the
clamp may damage the device.
Note 4: An internal clamp limits the HGATE pin to a minimum of 10V
above and a diode below OUT. Driving this pin to voltages beyond the
clamp may damage the device.
Note 5: Thermal resistance is specified when the exposed pad is soldered
to a 3" × 4.5", four layer, FR4 board.