Datasheet

LTM4624
13
4624fb
For more information www.linear.com/LTM4624
APPLICATIONS INFORMATION
Stability Compensation
The LTM4624’s internal compensation loop is designed and
optimized for use with low ESR ceramic output capacitors.
Table 5 is provided for most application requirements. In
case a bulk output capacitor is required for output ripple
or dynamic transient spike reduction, an additional 10pF
to 15pF feedforward capacitor (C
FF
) is needed between
the V
OUT
and FB pins. The LTpowerCAD design tool is
available for control loop optimization.
RUN Enable
Pulling the RUN pin to ground forces the LTM4624 into
its shutdown state, turning off both power MOSFETs and
most of its internal control circuitry. Bringing the RUN pin
above 0.7V turns on the internal reference only, while still
keeping the power MOSFETs off. Increasing the RUN pin
voltage above 1.25V will turn on the entire chip.
Low Input Application
The LTM4624 module has a separate SV
IN
pin which
makes it suitable for low input voltage applications down
to 2.375V. The SV
IN
pin is the single input of the whole
control circuitry while the V
IN
pin is the power input which
directly connects to the drain of the top MOSFET. In most
applications where V
IN
is greater than 4V, connect SV
IN
directly to V
IN
with a short trace. An optional filter, con-
sisting of a resistor (1Ω to 10Ω) between SV
IN
and V
IN
along with a 0.1µF bypass capacitor between SV
IN
and
ground, can be placed for additional noise immunity. This
filter is not necessary in most cases if good PCB layout
practices are followed (see Figure 19). In a low input
voltage (2.375V to 4V) application, or to reduce power
dissipation by the internal bias LDO, connect SV
IN
to an
external voltage higher than 4V with a 0.1µF local bypass
capacitor. Figure 21 shows an example of a low input
voltage application. Please note the SV
IN
voltage cannot
go below the V
OUT
voltage.
Thermal Considerations and Output Current Derating
The thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those param
-
eters defined by JESD 51-12 and are intended for use with
finite element analysis (FEA) software modeling tools that
leverage the outcome of thermal modeling, simulation,
and correlation to hardware evaluation performed on a
µModule package mounted to a hardware test board.
The motivation for providing these thermal coefficients is
found in JESD 51-12 (Guidelines for Reporting and Using
Electronic Package Thermal Information).
Many designers may opt to use laboratory equipment
and a test vehicle such as the demo board to anticipate
the µModule regulator’s thermal performance in their ap
-
plication at various electrical and environmental operating
conditions to compliment any FEA activities. Without FEA
software, the thermal resistances reported in the Pin Con
-
figuration section are, in and of themselves, not relevant to
providing guidance of thermal per
formance; instead, the
derating cur
ves provided in this data sheet can be used
in a manner that yields insight and guidance pertaining to
one’s application usage, and can be adapted to correlate
thermal performance to one’s own application.
The Pin Configuration section gives four thermal coeffi
-
cients explicitly defined in JESD 51-12; these coefficients
are quoted or paraphrased below:
1.
θ
JA
, the thermal resistance from junction to ambient, is
the natural convection junction-to-ambient air thermal
resistance measured in a one cubic foot sealed enclo
-
sure. This environment is sometimes referred to as
“still air” although natural convection causes the air to
move. This value is determined with the part mounted
to a 95mm × 76mm PCB with four layers.
2. θ
JCbottom
, the thermal resistance from junction to the
bottom of the product case, is determined with all of
the component power dissipation flowing through the
bottom of the package. In the typical µModule regulator,
the bulk of the heat flows out the bottom of the pack
-
age, but there is always heat flow out into the ambient
environment. As a result, this thermal resistance value
may be useful for comparing packages, but the test
conditions
don’t
generally match the user’s application.