Datasheet

6
dc1840afa
DEMO MANUAL DC1840A
Demonstration circuit 1682a operation
Figure 7. DC1682A LTC4271 I
2
C and Address Connections
I
2
C Communication and Addressing
The LTC4271 internal registers are accessed via I
2
C to read
and/or write configuration, status, and interrupt registers.
The I
2
C lines SDAOUT, SDAIN and SCL connect to the
34-pin connector (Figure 7). Subsequently, the I
2
C bus
is accessed on the DC1680A.
The LTC4270/LTC4271 chipset has an address of
(A
6
10A
3
A
2
A
1
A
0
b), where A
6
, A
3
, A
2
, A
1
, and A
0
are the
logic state of the AD6, AD3, AD2, AD1, and AD0 pins
respectively. On the DC1682A, AD0 and AD1 are tied low
with pull-down resistors. AD2, AD3 and AD6 are brought
out to the 34-pin connector (Figure 7) and set with three
switches on the DC1680A.
I/O LED Indicators
The DC1682A features four LEDs to indicate the states of
the LTC4270/LTC4271 chipset general purpose input output
pins. These pins are configured as inputs or outputs via
I
2
C. GP1 and GP0 are referenced to DGND and driven by
the LTC4271 when set as outputs (Figure 8). XIO0 and
XIO1 are referenced to V
EE
and are driven by the LTC4270
when set as outputs (Figure 9). J2 provides test points
for access to these I/Os.
Figure 8. DC1682A, LTC4270 General Purpose I/O LED Indicators
Figure 9. DC1682A, LTC4271 General Purpose I/O LED Indicators
Figure 10. DC1682A AUTO and MID Jumpers
DGND
SDAOUT
SDAIN
SCL
INT
SDAOUT
SDAIN
SCL
INT
AD6
AD3
AD2
AD1
AD0
AD6
AD3
AD2
TO 34-PIN
CONNECTOR
LTC4271
R7
0Ω
DC1840A F07
R8
0Ω
R9
0Ω
V
DD33
GP1
GP0
DGND
J2, PIN 5
J2, PIN 6
2 2
1 1
LTC4271
DC1840A F09
R28
560Ω
R29
560Ω
D3
GRN
GP0
D2
GRN
GP1
V
DD33
V
DD33
AUTO
MID
DGND
J2, PIN 3
J2, PIN 4
LTC4271
DC1840A F10
JP1 JP2
AUTO
HI
LO
MID
HI
LO
AGND
XIO1
XIO0
V
EE
J2, PIN 9
J2, PIN 10
V
EE
LTC4270
DC1840A F08
R30
27k
R31
27k
D5
GRN
XIO0
D4
GRN
XIO1
Q13B
BC846AS
Q13A
BC846AS
R33
220k
3
4
5
R32
220k