Datasheet

LTC4366-1/LTC4366-2
436612fd
For more information www.linear.com/LTC4366
19
applicaTions inForMaTion
V
DD
SD
R1
470k
R2
100k
OUT
C
G
2nF
GATE
M1
IXTH12N100L
SD FB
C
T
3.3nF
C1
0.47µF
R
FB1
12.4k
V
OUT
0.5A
(200V CLAMP)
V
IN
160V (RECTIFIED 110V AC)
100V TO 800V
R
FB2
2M
436612 F07
R
SS
412k
R
G
10Ω
R
IN
4.64M
Q1
BF722
LTC4366-2
TIMER BASEV
SS
DANGER! Lethal Voltages Present
Figure 7. Rectified 110V AC Supply Protected from 220V AC
times time or P
2
t. Knowing the power we then adjust
the time using the timer capacitor to limit the P
2
t during
overvoltage. In this example the MOSFET data sheet has
a 6400W
2
s P
2
t for a 10ms single pulse.
In this application 250V minus 43V is applied across the
MOSFET at 3A. If the power is applied for less than 16.5ms
then MOSFET P
2
t limit is not exceeded:
P = (250V – 43V) • 3A = 621W
P
2
t = (621W)
2
• 16.5ms = 6363W
2
s
Prior to the moment when the output is regulated at 43V,
the output is ramping from 28V to 43V. This ramp time is
based on the 20µA gate current charging the 10nF capaci
-
tor. Using the equation for ramp time:
∆t =
C
G
•
∆
V
I
G
=
10nF • 15V
20µA
= 7.5m
s
To be safe we set the overvoltage time to 10ms. We set the
regulation time to be 2.5ms (the remainder of the 10ms
overvoltage time minus the ramp time). In this example
it is assumed the 250V overvoltage is a constant DC volt
-
age for 10ms. This duration exceeds Mil-Std-1275 which
specifies a 70µs surge to 250V that decays in 1.6ms. Us-
ing the following equation (based on charging with 9µA)
to set the C
T
:
C
T
=I
T
•
∆
t
∆V
= 9µA •
2.5ms
2.5V
≈ 10nF
In order to limit the SD pin current (10mA max) a collector
resistor, R1, in series with Q2 is required. The maximum
value for this resistor is around 5M. This requirement oc
-
curs when the pull-down is required to sink 1.6µA from
SD and V
DD
is clamped at 12V. High valued resistors are
susceptible to leakage currents so we chose a 470k resistor
for R1. Resistor R2 provides ESD protection for Q2’s base.
The gate resistor R
G
limits the parasitic trace capacitance
on Q1’s gate node that could lead to parasitic MOSFET
self-oscillation. The recommended value for R
G
is 10Ω.
High Voltage Application
In Figure 7 the circuit accepts 110V AC (rectified to 160V)
and protects the load from accidental connection to 220V
AC by limiting the output to less than 200V. The circuit has
a 100V to 800V V
IN
operating range where the FET break-
down voltage limits the maximum input voltage. The C1
is set to 0.47µF to provide a bypass for the charge pump
that is large enough to provide good noise immunity from
outside voltage transients. The timer capacitor is sized to
give a 1ms overvoltage regulation time that keeps the P
2
t
below the 640W
2
s specified for this MOSFET.