Datasheet

LTC4366-1/LTC4366-2
436612fd
For more information www.linear.com/LTC4366
14
applicaTions inForMaTion
the V
DD
pin, and finally the current from the V
SS
pin (see
Figure 5.).
V
IN(MIN)
= (I
VDD
• R
IN
) + V
D
+ V
TH
+ V
C1
+ (I
VSS
• R
SS
)
Using the Electrical Characteristics table for above
parameters:
V
C1
= V
UVLO2
= 4.75V (UVLO2 threshold)
I
VDD
= I
VDD(STHI)
= 9µA (I
VDD
start-up, gate high)
I
VSS
= I
VSS(AMP)
= 45µA (I
VSS
w/regulation amp)
V
D
= 0.58V
V
IN(MIN)
= (9µA • R
IN
) + 0.58V + V
TH
+ 4.75V + (45µA•R
SS
)
When the MOSFET gate is fully enhanced, the OUT pin
voltage is equal to the supply voltage. This places another
constraint on the minimum supply voltage because the
charge pump increases the V
SS
current to 160µA. The C1
voltage is assumed to be clamped at 5.7V. These values
are specified as V
Z(OUT)
and I
VSS(CP)
(charge pump on)
in the table of Electrical Characteristics:
V
IN(MIN)
= V
Z(OUT)
+ (I
VSS(CP)
• R
SS
)
or
V
IN(MIN)
= 5.7V + (160µA • R
SS
)
The last V
IN(MIN)
equation sets the maximum value for
R
SS
. After choosing R
SS
the maximum value for R
IN
(for
that particular R
SS
) is calculated from the first V
IN(MIN)
equation:
R
SS(MAX)
=
V
IN(MIN)
– 5.7V
160µA
R
IN(MAX)
=
V
IN(MIN)
– 4.75V – 0.58V – V
TH
– 45µA • R
SS
( )
9µA
These two equations maximize the values of R
SS
and
R
IN
(reducing power dissipation) while still providing
the necessary V
C1
voltage to turn the charge pump on.
Increasing the supply voltage beyond the minimum sup-
ply voltage increases the current and power in R
SS
while
reducing the time required to charge C1. Conditions that
may require an even smaller R
SS(MAX)
will be discussed
in the Maximum Supply Start-Up section.
Maximum Supply Start-Up
The maximum overvoltage supply may also exist during
start-up. The overvoltage protection circuitry has to wake
up before high voltage is passed to the load. Dynamically
the GATE is ramping up while C1 is charging. Capacitor
C1 must charge to the 2.55V UVLO1 threshold to turn on
the regulation amplifier and reference before the OUT pin
voltage exceeds the overvoltage regulation point, V
REG
.
These conditions may reduce the value of R
SS
below the
maximum value dictated by the minimum supply start-up
discussed above.
When current in R
SS
exceeds the current sourced from
the V
SS
pin (essentially I
RIN
), the capacitor C1 begins to
charge. The voltage at the V
SS
pin when I
RIN
= I
RSS
is now
labeled V
SS(MATCH)
. The V
SS
pin voltage is the center of a
voltage divider between R
IN
and R
SS
after the Zener clamp
voltage from V
DD
to V
SS
is subtracted from the supply.
V
SS(MATCH)
=
R
SS
R
SS
+R
IN
• V
IN(MAX)
– V
Z(VDD)
( )
As V
IN
increases the V
SS(MATCH)
voltage increases. If the
match voltage exceeds the overvoltage regulation point
(V
REG
), then load is unprotected. This is true because
C1 will still need to charge to 2.55V while V
SS
already
M1
GATE
D1
7.5µA
C
G
V
DD
R
IN
I
RIN
V
IN
Z3
5.7V
Z1
12V
I
BIAS
I
SHUNT2
9µAI
SHUNT1
I
C1
I
RSS
V
OUT
OUT
R
LOAD
436612 F05
R
SS
V
SS
CIRCUITS
LOGIC
TIMER
V
C1
C1
+
–
Figure 5. Simplified Block Diagram