Datasheet

LTC4366-1/LTC4366-2
436612fd
For more information www.linear.com/LTC4366
12
applicaTions inForMaTion
Starting up with a supply voltage insufficient to charge
C1 with large load current may result in overheating the
MOSFET and subsequent damage. While the gate and
output are ramping the drop across the MOSFET is the
input supply minus the output. If the supply is lower than
necessary to charge C1, then the output fails to ramp higher
than the supply minus the threshold of the MOSFET. This
3V to 5V MOSFET drop with high load current will result in
power dissipation without any protection or timeout limit.
Overvoltage Fault
The LTC4366 prevents an overvoltage on the input supply
from reaching the load. Normally, the pass transistor is
fully on, powering the load with very little voltage drop.
As the input voltage increases the OUT voltage increases
until it reaches the regulation point (V
REG
). From that
point any further voltage increase is dropped across the
MOSFET. Note the MOSFET is still on so the LTC4366 allows
uninterrupted operation during a short overvoltage event.
The V
REG
point is configured with the two FB resistors, R
FB1
and R
FB2
. The regulation amplifier compares the FB pin to
a threshold 1.23V below the OUT pin. During regulation
the drop across R
FB1
is 1.23V, while the remainder of the
V
REG
voltage is dropped across R
FB2
.
When the output is at the regulation point a timer is started
to prevent excessive power dissipation in the MOSFET.
Normally the TIMER pin is held low with a 1.8µA pull-
down current. During regulation the TIMER pin charges
with 9µA. If the regulation point is held long enough for
the TIMER pin to reach 2.8V then an overvoltage fault is
latched. The equation for setting the timer capacitor is:
C
T
=
3.5 • t nF / ms
[ ]
Depending on which version, the part will cool down and
self start (LTC4366-2), or remain latched off until the SD
pin activates a shutdown followed by a start-up command
(LTC4366-1). The cool-down time is typically nine seconds
which provides a very low pulsed power duty cycle.
Starting up with an input supply overvoltage and full
load current does increase the power dissipation in the
MOSFET well beyond the case for an overvoltage surge.
During the gate and output ramp up, the partial supply
voltage (at full current) is dropped across the MOSFET.
After start-up the normal overvoltage surge (with timeout)
occurs before the shutting off the MOSFET. The Design
Example section only considers the normal overvoltage
surge for safe operating area (SOA) calculations for the
MOSFET. Start-up into overvoltage will require additional
SOA considerations.
Shutdown
The LTC4366 has a low current (<20µA) shutdown state
that turns off the pass FET by tying the GATE and OUT pins
together with a switched resistor. In the normal operating
condition, the SD pin is pulled up to the V
DD
pin voltage
with a 1.6µA current source. Tie the SD pin to V
DD
when
the shutdown state is not used.
Bringing the SD pin more than 1.5V below V
DD
pin volt-
age for greater than the 700µs filter time activates the
shutdown state. This filter time prevents unwanted activa-
tion of shutdown during transients. The SD pin is diode
clamped 0.7V below V
SS
which requires current limiting
(maximum 10mA) on the pull-down device. One way to
limit the current is to connect an external 470k resistor in
series with the open-collector pull-down device. Activat
-
ing the external pull-down overcomes the internal 1.6µA
pull-up current source and allows the
SD pin to cross the
shutdown threshold.