Datasheet

ManualsBrandsLINEAR TECHNOLOGY ManualsDev KitsPCB design board

LTC4266A/LTC4266C

4266acfc

LTPoE

PSE Switches/Routers

LTPoE

PSE Midspans

IEEE 802.3at Type 1 PSE Switches/Routers

IEEE 802.3at Type 1 PSE Midspans

APPLICATIONS

FEATURES DESCRIPTION

Quad PoE/PoE

/LTPoE

PSE Controller

The LTC

4266A is a quad power sourcing equipment (PSE)

controller capable of delivering up to 90W of LTPoE

power to a compatible LTPoE

powered device (PD). A

proprietary detection/classification scheme allows mutual

identification between a LTPoE

PSE and LTPoE

while remaining compatible and interoperable with existing

Type 1 (13W) and Type 2 (25.5W) PDs. The LTC4266A

feature set is a superset of the popular LTC4266. These

PSE controllers feature low R

external MOSFETs and

0.25 sense resistors which are especially important at

the LTPoE

current levels to maintain the lowest possible

heat dissipation.

The LTC4266C targets fully automatic PSE systems power-

ing Type 1 (up to 13W) PDs.

Advanced power management features include: 14-bit

current monitoring ADCs, DAC-programmable current

limit, and versatile quick shutdown of preselected ports.

Advanced power management host software is available

under a no-cost license. PD discovery uses a proprietary

dual-mode 4-point detection mechanism ensuring excellent

immunity from false PD detection. The LTC4266 includes

an I

C serial interface operable up to 1MHz.

The LTC4266 is available in multiple power grades al-

lowing delivered PD power of 13W, 25W, 38.7W, 52.7W,

70W and 90W. These controllers are available in a 38-lead

5mm × 7mm QFN package.

Four Independent PSE Channels

Compliant with IEEE 802.3at Type 1 and 2

Low Power Dissipation

0.25Ω Sense Resistance Per Channel

Very High Reliability 4-Point PD Detection

2-Point Forced Voltage

2-Point Forced Current

High Capacitance Legacy Device Detection

1MHz I

C Compatible Serial Control Interface

Midspan Backoff Timer

Supports 2-Pair and 4-Pair Output Power

Available in Multiple Power Grades

LTC4266A-1: LTPoE

™ 38.7W

LTC4266A-2: LTPoE

52.7W

LTC4266A-3: LTPoE

70W

LTC4266A-4: LTPoE

90W

LTC4266C: PoE 13W

Available in 38-Lead 5mm × 7mm QFN Package

TYPICAL APPLICATION

Complete 4-Port Ethernet High Power Source

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

LTPoE

and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks

are the property of their respective owners.

4266 TA01

SCL

SDAIN

SDAOUT

AD0

AD1

AD2

AD3

AGND V

SENSE1

–50V

1µFSMAJ58A

GATE1 OUT1 OUT2 OUT3SENSE2 GATE2 SENSE3 GATE3 SENSE4 GATE4 OUT4

PORT1

–50V

0.22µF 100V

S1B

PORT2

PORT3

PORT4

DGND

INT SHDN1 SHDN2 AUTO MSD RESETSHDN3 SHDN4 MID

0.1µF

3.3V

LTC4266

Summary of content (30 pages)

PAGE 1
LTC4266A/LTC4266C Quad PoE/PoE+/LTPoE++ PSE Controller DESCRIPTION FEATURES n n n n n n n n n n Four Independent PSE Channels Compliant with IEEE 802.3at Type 1 and 2 Low Power Dissipation 0.
PAGE 2
LTC4266A/LTC4266C OUT1 AUTO MSD RESET MID TOP VIEW INT Supply Voltages (Note 1) AGND – VEE ........................................... –0.3V to 80V DGND – VEE ........................................... –0.3V to 80V VDD – DGND ......................................... –0.3V to 5.5V Digital Pins SCL, SDAIN, SDAOUT, INT, SHDNn, MSD, ADn, RESET, AUTO, MID........... DGND –0.3V to VDD + 0.3V Analog Pins GATEn, SENSEn, OUTn .......... VEE –0.3V to VEE + 80V Operating Temperature Range LTC4266I ...........
PAGE 3
LTC4266A/LTC4266C ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless otherwise noted. (Notes 3, 4) SYMBOL PARAMETER CONDITIONS VEE Main PoE Supply Voltage AGND – VEE For IEEE Type 1 Compliant Output For IEEE Type 2 Compliant Output For LTPoE++ Compliant Output l l l 45 51 54.
PAGE 4
LTC4266A/LTC4266C ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless otherwise noted. (Notes 3, 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Current Sense VCUT VLIM VLIM VLIM Overcurrent Sense Voltage VSENSEn – VEE hpen = 0Fh, cutn[5:0] ≥ 4 (Note 12) cutrng = 0 cutrng = 1 l l 9 4.5 9.38 4.69 9.75 4.
PAGE 5
LTC4266A/LTC4266C ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless otherwise noted.
PAGE 6
LTC4266A/LTC4266C ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless otherwise noted.
PAGE 7
LTC4266A/LTC4266C TYPICAL PERFORMANCE CHARACTERISTICS Power-On Sequence in AUTO Pin Mode 802.3af Classification in AUTO Pin Mode Powering Up into a 180μF Load 10 GND GND FORCED CURRENT DETECTION 0 GND PORT VOLTAGE (V) FORCED VOLTAGE DETECTION –20 –30 –40 LOAD FULLY CHARGED –18.4 VEE PORT CURRENT 200 mA/DIV 802.3af CLASSIFICATION PORT 1 VDD = 3.3V VEE = –54V POWER ON –50 –60 VDD = 3.3V VEE = –54V PORT VOLTAGE 20V/DIV –10 FOLDBACK 0mA GATE VOLTAGE 10V/DIV VEE VEE PORT 1 VDD = 3.
PAGE 8
LTC4266A/LTC4266C TYPICAL PERFORMANCE CHARACTERISTICS 802.3af ILIM Threshold vs Temperature 163 648 161 644 160 640 159 636 423 105.75 105.00 –40 0 158 –40 420 120 40 80 TEMPERATURE (°C) 0 40 80 TEMPERATURE (°C) 4266AC G10 DC Disconnect Threshold vs Temperature 384 2.0000 381 1.9375 378 93.75 375 93.00 –40 0 7.75 1.8750 7.50 1.8125 7.25 1.7500 –40 372 120 80 40 TEMPERATURE (°C) 8.00 VDD = 3.3V VEE = –54V RSENSE = 0.
PAGE 9
LTC4266A/LTC4266C TYPICAL PERFORMANCE CHARACTERISTICS ADC Noise Histogram Current Readback in Slow Mode ADC INTEGRAL NONLINEARITY (LSBs) 250 200 BIN COUNT 600 1.0 VSENSEn – VEE = 110.4mV 150 100 50 0 6139 500 400 0 6145 200 100 6147 0 0 50 100 150 200 250 300 350 400 450 500 CURRENT SENSE RESISTOR INPUT VOLTAGE (mV) 500 BIN COUNT 400 300 200 –0.5 100 50 60 0 0.5 0 –0.5 –1.
PAGE 10
LTC4266A/LTC4266C TEST TIMING DIAGRAMS tDET CLASSIFICATION FORCEDVOLTAGE FORCED-CURRENT tME 0V VPORTn tMEL VOC VMARK 15.5V VCLASS 20.5V tCLE tCLE PD CONNECTED tCLEON tPON VEE INT 4266AC F01 Figure 1. Detect, Class and Turn-On Timing in AUTO Pin or Semi-auto Modes VLIM VCUT VSENSEn TO VEE VSENSEn TO VEE 0V VMIN tSTART, tICUT INT INT tMPS tDIS 4266AC F02 4266AC F03 Figure 3. DC Disconnect Timing Figure 2.
PAGE 11
SDA SCL 1 0 1 0 AD3 AD2 AD1 AD0 R/W ACK A7 A5 A4 A3 A2 A1 A4 A0 ACK ACK BY SLAVE A3 A2 A0 ACK D7 ACK BY SLAVE A1 0 0 D6 D5 D3 FRAME 3 DATA BYTE D4 D2 FRAME 1 SERIAL BUS ADDRESS BYTE D6 D5 D3 D1 D0 ACK NO ACK BY MASTER D2 4266AC F06 STOP BY MASTER FRAME 2 DATA BYTE D4 D0 ACK ACK BY SLAVE D1 ACK BY SLAVE AD3 AD2 AD1 AD0 R/W ACK D7 REPEATED START BY MASTER 1 Figure 7.
PAGE 12
LTC4266A/LTC4266C I2C TIMING DIAGRAMS SCL SDA 0 1 0 AD3 AD2 AD1 AD0 R/W ACK D7 START BY MASTER D6 D5 D4 D3 ACK BY SLAVE D2 D1 D0 ACK STOP BY MASTER NO ACK BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 DATA BYTE 4266AC F08 Figure 8.
PAGE 13
LTC4266A/LTC4266C PIN FUNCTIONS RESET: Chip Reset, Active Low. When the RESET pin is low, the LTC4266A/LTC4266C is held inactive with all ports off and all internal registers reset to their power-up states. When RESET is pulled high, the LTC4266A/LTC4266C begins normal operation. RESET can be connected to an external capacitor or RC network to provide a power turn-on delay. Internal filtering of the RESET pin prevents glitches less than 1μs wide from resetting the LTC4266A/ LTC4266C.
PAGE 14
LTC4266A/LTC4266C PIN FUNCTIONS GATE4: Port 4 Gate Drive. GATE4 should be connected to the gate of the external MOSFET for port 4. When the MOSFET is turned on, the gate voltage is driven to 12V (typ) above VEE. During a current limit condition, the voltage at GATE4 will be reduced to maintain constant current through the external MOSFET. If the fault timer expires, GATE4 is pulled down, turning the MOSFET off and recording a t CUT or tSTART event. If the port is unused, float the GATE4 pin.
PAGE 15
LTC4266A/LTC4266C OPERATION Overview Power over Ethernet, or PoE, is a standard protocol for sending DC power over copper Ethernet data wiring. The IEEE group that administers the 802.3 Ethernet data standards added PoE powering capability in 2003. This original PoE spec, known as 802.3af, allowed for 48V DC power at up to 13W. This initial spec was widely popular, but 13W was not adequate for some requirements. In 2009, the IEEE released a new standard, known as 802.
PAGE 16
LTC4266A/LTC4266C OPERATION PoE Basics New in 802.3at Common Ethernet data connections consist of two or four twisted pairs of copper wire (commonly known as CAT-5 cable), transformer-coupled at each end to avoid ground loops. PoE systems take advantage of this coupling arrangement by applying voltage between the center-taps of the data transformers to transmit power from the PSE to the PD without affecting data transmission. Figure 10 shows a high-level PoE system schematic. The newer 802.
PAGE 17
LTC4266A/LTC4266C OPERATION Extended Power LTPoE++ The LTC4266A adds the capability to autonomously deliver up to 90W of power to the PD. LTPoE++ PDs may forgo 802.3 LLDP support and rely solely on the LTPoE++ Physical Classification to negotiate power with LTPoE++ PSEs; this greatly simplifies high-power PD implementations. LTPoE++ classification may be optionally enabled for the LTC4266A by setting both the High Power Enable and LTPoE++ Enable bits.
PAGE 18
LTC4266A/LTC4266C APPLICATIONS INFORMATION Operating Modes The LTC4266A/LTC4266C include four independent ports, each of which can operate in one of four modes: manual, semi-auto, AUTO pin, or shutdown. Table 2.
PAGE 19
LTC4266A/LTC4266C APPLICATIONS INFORMATION The IEEE specification requires that a valid PD have a common-mode resistance of 25k ±5% at any port voltage below 10V. The PSE must accept resistances that fall between 19k and 26.5k, and it must reject resistances above 33k or below 15k (shaded regions in Figure 11). The PSE may choose to accept or reject resistances in the undefined areas between the must-accept and must-reject ranges.
PAGE 20
LTC4266A/LTC4266C APPLICATIONS INFORMATION Behavior in AUTO pin mode is similar to semi-auto; however, after Detect Good is reported and the port is classified (if classification is enabled), it is automatically powered on without further intervention. In standalone (AUTO pin) mode, the ICUT and ILIM thresholds are automatically set; see the Reset and the AUTO/MID Pin section for more information.
PAGE 21
LTC4266A/LTC4266C APPLICATIONS INFORMATION 802.3at 2-Event Classification The 802.3at specification defines two methods of classifying a Type 2 PD. The LTC4266A supports 802.3at 2-event classification. The LTC4266C does not support 2-event classification. One method adds extra fields to the Ethernet LLDP data protocol; although the LTC4266A/LTC4266C is compatible with this classification method, it cannot perform classification directly since it doesn’t have access to the data path.
PAGE 22
LTC4266A/LTC4266C APPLICATIONS INFORMATION Current Limit Each LTC4266A/LTC4266C port includes two current limiting thresholds (ICUT and ILIM), each with a corresponding timer (tCUT and tLIM). Setting the ICUT and ILIM thresholds depends on several factors: the class of the PD, the voltage of the main supply (VEE), the type of PSE (Type 1 or Type 2), the sense resistor (0.5Ω or 0.25Ω), the SOA of the MOSFET, and whether or not the system is required to implement class enforcement.
PAGE 23
LTC4266A/LTC4266C APPLICATIONS INFORMATION The LTC4266A/LTC4266C will support current levels well beyond the maximum values in the 802.3at specification. The shaded areas in Table 6 indicate settings that may require a larger external MOSFET, additional heat sinking, or enabling tLIM . MOSFET Fault Detection LTC4266A/LTC4266C PSE ports are designed to tolerate significant levels of abuse, but in extreme cases it is possible for the external MOSFET to be damaged.
PAGE 24
LTC4266A/LTC4266C APPLICATIONS INFORMATION they are staggered by at least 0.55μs to help reduce voltage transients on the main supply. If a port is turned off via MSD, the corresponding Detection and Classification Enable bits are cleared, so the port will remain off until the host explicitly re-enables detection. SERIAL DIGITAL INTERFACE Overview The LTC4266A/LTC4266C communicates with the host using a standard SMBus/I2C 2-wire interface.
PAGE 25
LTC4266A/LTC4266C APPLICATIONS INFORMATION L3 100μH SUMIDA CDRH5D28-101NC L4 10μH SUMIDA CDRH4D28-100NC D28 B1100 3.3V AT 400mA C76 10μF 63V + R51 4.7k 1% C78 0.22μF 100V 5 VCC C77 0.22μF 100V 1 R58 10Ω R60 10Ω C74 100μF 6.3V C75 10μF 16V R53 4.7k 1% R54 56k C79 2200pF ITH/RUN C73 10μF 6.3V R52 3.32k 1% Q13 FMMT723 NGATE 6 Q14 FMMT723 Q15 FDC2512 LTC3803 3 VFB SENSE 4 GND 2 R57 1k R55 806Ω 1% R59 0.100Ω 1%, 1W R56 47.5k 1% VEE 4266AC F15 Figure 15.
PAGE 26
LTC4266A/LTC4266C APPLICATIONS INFORMATION 0.1μF 0.1μF I2C ADDRESS VDD LTC4266 INT SCL SDAIN SDAOUT AD0 AD1 AD2 AD3 DGND AGND 0100000 VDD LTC4266 INT SCL SDAIN SDAOUT AD0 AD1 AD2 AD3 DGND AGND 0100001 VDD LTC4266 INT SCL SDAIN SDAOUT AD0 AD1 AD2 AD3 DGND AGND 0100010 0.1μF 2k U2 200Ω VDD CPU U1 SCL 2k 200Ω SDA 0.1μF HCPL-063L TO CONTROLLER U3 200Ω 200Ω SMBALERT 0.1μF 0.1μF GND CPU U1: FAIRCHILD NC7WZ17 U2, U3: AGILENT HCPL-063L HCPL-063L 0.1μF ISOLATED 3.
PAGE 27
LTC4266A/LTC4266C APPLICATIONS INFORMATION External MOSFET ESD/Cable Discharge Protection Careful selection of the power MOSFET is critical to system reliability. LTC recommends either Fairchild IRFM120A, FDT3612, FDMC3612 or Philips PHT6NQ10T for their proven reliability in Type 1 and Type 2 PSE applications. Non-standard applications that provide more current than the 850mA IEEE maximum may require heat sinking and other MOSFET design considerations.
PAGE 28
LTC4266A/LTC4266C PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UHF Package 38-Lead Plastic QFN (5mm × 7mm) (Reference LTC DWG # 05-08-1701 Rev C) 0.70 p 0.05 5.50 p 0.05 5.15 ± 0.05 4.10 p 0.05 3.00 REF 3.15 ± 0.05 PACKAGE OUTLINE 0.25 p 0.05 0.50 BSC 5.5 REF 6.10 p 0.05 7.50 p 0.05 RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 p 0.10 0.75 p 0.05 PIN 1 NOTCH R = 0.30 TYP OR 0.
PAGE 29
LTC4266A/LTC4266C REVISION HISTORY REV DATE DESCRIPTION A 8/11 Changed Gate Typical voltage to 12V. PAGE NUMBER Changed SCL, SDAIN VIL B C 02/12 08/12 to 1.0V (I2C compliance). 3, 14, 21 4 Table 4 (Class) reference and caption changed to Table 5. 20 Power Supplies and Bypassing section changed to –45 for Type 1 minimum and –51 for Type 2 minimum. 24 Related Parts Table CUT/LIM changed to ICUT/ILIM. Change LTPoE++ power levels from 35W, 45W to 38.7W, 52.
PAGE 30
LTC4266A/LTC4266C TYPICAL APPLICATION ISOLATED 3.3V ISOLATED GND 0.1μF DGND AGND 2k U2 200Ω FB1 SCL 1/4 SDAIN LTC4266 SDAOUT INT VDD CPU U1 SCL VEE 2k 200Ω 1μF 100V X7R TO CONTROLLER 0.22μF 100V X7R VDD SENSE GATE OUT FB2 S1B RS 0.25Ω SDA Q1 HCPL-063L U3 SMAJ58A 200Ω –48V ISOLATED S1B RJ45 CONNECTOR T1 t 200Ω INTERRUPT t t t t 0.01μF 200V 75Ω 0.01μF 200V 75Ω 75Ω 75Ω 1 2 3 4 5 6 7 8 t PHY 0.1μF GND CPU t t t t t HCPL-063L (NETWORK PHYSICAL LAYER CHIP) 0.