Datasheet

LTC4266A/LTC4266C
10
4266acfc
TEST TIMING DIAGRAMS
Figure 1. Detect, Class and Turn-On Timing in AUTO Pin or Semi-auto Modes
Figure 2. Current Limit Timing
Figure 3. DC Disconnect Timing
Figure 4. Shut Down Delay Timing Figure 5. I
2
C Interface Timing
V
PORTn
INT
V
OC
V
EE
t
DET
t
ME
t
MEL
V
MARK
V
CLASS
15.5V
20.5V
t
CLE
t
CLE
t
CLEON
PD
CONNECTED
0V
4266AC F01
FORCED-CURRENT
CLASSIFICATION
t
PON
FORCED-
VOLTAGE
V
LIM
V
CUT
0V
V
SENSEn
TO V
EE
INT
4266AC F02
t
START
, t
ICUT
V
MIN
V
SENSEn
TO V
EE
INT
t
DIS
t
MPS
4266AC F03
V
GATEn
V
EE
MSD or
SHDNn
t
SHDN
t
MSD
4266AC F04
SCL
SDA
t
1
t
2
t
3
t
r
t
f
t
5
t
6
t
7
t
8
t
4
4266AC F05