Datasheet

LTC2364-16
14
236416fa
APPLICATIONS INFORMATION
to the maximum voltage relationships described in the
Absolute Maximum Ratings section. The LTC2364
-16
has a power-on-reset (POR) circuit that will reset the
LTC2364-16 at initial power-up or whenever the power
supply voltage drops below 1V. Once the supply voltage
re-enters the nominal supply voltage range, the POR will
reinitialize the ADC. No conversions should be initiated
until 20µs after a POR event to ensure the reinitialization
period has ended. Any conversions initiated before this
time will
produce invalid results.
TIMING AND CONTROL
CNV Timing
The LTC2364-16 conversion is controlled by CNV. A ris-
ing edge on CNV will start a conversion and power up
the LTC2364-16. Once a conversion has been initiated,
it cannot be restarted until the conversion is complete.
For optimum performance, CNV should be driven by a
clean low jitter signal. Converter status is indicated by the
BUSY output which
remains high while the conversion is
in progress. To ensure that no errors occur in the digitized
results, any additional transitions on CNV should occur
within 40ns from the start of the conversion or after the
conversion has been completed. Once the conversion has
completed, the LTC2364-16 powers down and begins
acquiring the input signal.
Acquisition
A proprietary sampling architecture allows the LTC2364-16
to begin acquiring
the input signal for the next conver-
sion 527ns after the start of the current conversion. This
extends the acquisition time to 3.460µs, easing settling
requirements and allowing the use of extremely low power
ADC drivers. (Refer to the Timing Diagram.)
Internal Conversion Clock
The LTC2364-16 has an internal clock that is trimmed
to achieve a maximum conversion time of 3µs.
Auto Power-Down
The LTC2364-16 automatically
powers down after a
conversion has been completed and powers up once a
new conversion is initiated on the rising edge of CNV.
During power down, data from the last conversion can
be clocked out. To minimize power dissipation during
power down, disable SDO and turn off SCK. The auto
power-down feature will reduce the power dissipation of
the LTC2364-16 as the sampling frequency is reduced
.
Since power is consumed only during a conversion, the
LTC2364-16 remains powered down for a larger fraction of
the conversion cycle (t
CYC
) at lower sample rates, thereby
reducing the average power dissipation which scales with
the sampling rate as shown in Figure 9.
Figure 9. Power Supply Current of the LTC2364-16 Versus
Sampling Rate
SAMPLING RATE (kHz)
1
0
POWER SUPPLY CURRENT (mA)
0.2
0.4
0.6
0.8
1.2
1.6
1.0
1.4
50 100 150 200
I
VDD
236416 F09
250
I
OVDD
I
REF
DIGITAL INTERFACE
The LTC2364-16 has a serial digital interface. The flexible
OV
DD
supply allows the LTC2364-16 to communicate with
any digital logic operating between 1.8V and 5V, including
2.5V and 3.3V systems.
The serial output data is clocked out on the SDO pin when
an external clock is applied to the SCK pin if SDO is enabled.
Clocking out the data after the conversion will yield
the
best performance. With a shift clock frequency of at least
20MHz, a 250ksps throughput is still achieved. The serial
output data changes state on the rising edge of SCK and
can be captured on the falling edge or next rising edge of
SCK. D15 remains valid till the first rising edge of SCK.
The serial interface on the LTC2364-16 is simple and
straightforward to use
. The following sections describe the
operation of the LTC2364-16. Several modes are provided