Datasheet

8
LTC1418
FUNCTIONAL BLOCK DIAGRA
UU

W
14-BIT CAPACITIVE DAC
COMPREF AMP
2.5V REF
8k
REFCOMP
4.096V
2.5V
C
SAMPLE
C
SAMPLE
•
•
•
D13
D0
BUSY
CONTROL LOGIC
D2/(CLKOUT)

INTERNAL
CLOCK
SHDN
D0 (EXT/INT)D4 (EXTCLKIN) CONVST RD CS
ZEROING SWITCHES
D1/(D
OUT
)
NOTE: PIN NAMES IN PARENTHESES 
REFER TO SERIAL MODE
D3/(SCLK)
V
DD
: 5V
V
SS
: 0V FOR UNIPOLAR MODE
–5V FOR BIPOLAR MODE
A
IN
+
A
IN
–
V
REF
AGND
DGND
14
1418 BD
+
–
SUCCESSIVE APPROXIMATION
REGISTER
SHIFT
REGISTER
SER/PAR
MUX
APPLICATIONS INFORMATION
WUU
U
CONVERSION DETAILS
The LTC1418 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 14-bit parallel or serial output. The ADC
is complete with a precision reference and an internal
clock. The control logic provides easy interface to micro-
processors and DSPs (please refer to Digital Interface
section for the data format).
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion the successive
approximation register (SAR) is reset. Once a conversion
cycle has begun it cannot be restarted.
During the conversion, the internal differential 14-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit (LSB).
1418 F01
OUTPUT
LATCH
SAR
C
DAC
+
C
DAC
–
V
DAC
–
V
DAC
+
–
+
COMP
D13
D0
14
HOLD
HOLD
HOLD
A
IN
+
A
IN
–
ZEROING SWITCHES
C
SAMPLE
–
C
SAMPLE
+
HOLD
SAMPLE
SAMPLE
Figure 1. Simplified Block Diagram