Datasheet

4
LTC1418
TI I G CHARACTERISTICS
W
U
(Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
SAMPLE(MAX)
Maximum Sampling Frequency ● 200 kHz
t
CONV
Conversion Time ● 3.4 4 µs
t
ACQ
Acquisition Time ● 0.3 1 µs
t
ACQ
+ t
CONV
Acquisition Plus Conversion Time ● 3.7 5 µs
t
1
CS to RD Setup Time (Notes 9, 10) ● 0ns
t
2
CS↓ to CONVST↓ Setup Time (Notes 9, 10) ● 40 ns
t
3
CS↓ to SHDN↓ Setup Time to Ensure Nap Mode (Notes 9, 10) ● 40 ns
t
4
SHDN↑ to CONVST↓ Wake-Up Time from Nap Mode (Note 10) 500 ns
t
5
CONVST Low Time (Notes 10, 11) ● 40 ns
t
6
CONVST to BUSY Delay CL = 25pF ● 35 70 ns
t
7
Data Ready Before BUSY↑ 20 35 ns
● 15 ns
t
8
Delay Between Conversions (Note 10) ● 500 ns
t
9
Wait Time RD↓ After BUSY↑ ● –5 ns
t
10
Data Access Time After RD↓ C
L
= 25pF 15 30 ns
● 40 ns
C
L
= 100pF 20 40 ns
● 55 ns
t
11
Bus Relinquish Time 820 ns
Commercial ● 25 ns
Industrial
● 30 ns
t
12
RD Low Time ● t
10
ns
t
13
CONVST High Time 40 ns
t
14
Delay Time, SCLK↓ to D
OUT
Valid C
L
= 25pF (Note 9) ● 35 70 ns
t
15
Time from Previous Data Remain Valid After SCLK↓ C
L
= 25pF (Note 9) ● 15 25 ns
f
SCLK
Shift Clock Frequency (Notes 9, 10) 0 12.5 MHz
f
EXTCLKIN
External Conversion Clock Frequency (Notes 9, 10) 0.03 4.5 MHz
t
dEXTCLKIN
Delay Time, CONVST↓ to External Conversion Clock Input (Notes 9, 10) 533 µs
t
H SCLK
SCLK High Time (Notes 9, 10) 10 ns
t
L SCLK
SCLK Low Time (Notes 9, 10) 20 ns
t
H EXTCLKIN
EXTCLKIN High Time (Notes 9, 10) 250 ns
t
L EXTCLKIN
EXTCLKIN Low Time (Notes 9, 10) 250 ns
The ● denotes specifications which apply over the full operating
temperature range; all other limits and typicals T
A
= 25°C.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below V
SS
or above V
DD
, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below V
SS
or above V
CC
without latchup.
Note 4: When these pin voltages are taken below V
SS
they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below V
SS
without latchup. These pins are not clamped to V
DD
.
Note 5: V
DD
= 5V, V
SS
= 0V or –5V, f
SAMPLE
= 200kHz, t
r
= t
f
= 5ns unless
otherwise specified.
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended input with A
IN
–
grounded.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 00 and
1111 1111 1111 11.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling edge of CONVST starts a conversion. If CONVST
returns high at a critical point during the conversion, it can create small
errors. For best performance ensure that CONVST returns high either
within 2.1µs after the conversion starts or after BUSY rises.
Note 12: Pins 16 (D4/EXTCLKIN), 17 (D3/SCLK) and 20 (DO/EXT/INT) at
0V or 5V. See Power Shutdown.