Datasheet

25
LTC1418
APPLICATIONS INFORMATION
WUU
U
also allows operation when the SCLK frequency is very low
(less than 30kHz). To select the internal conversion clock
tie EXT/INT low. The external SCLK is applied to SCLK. RD
can be used to gate the external SCLK, such that data will
clock only after RD goes low and to three-state D
OUT
after
data transfer. If more than 16 SCLKs are provided, more
zeros will be filled in after the data word indefinitely.
LTC1418
BUSY
CONVSTCONVST
RD
EXTCLKIN
SCLK
EXT/INT
D
OUT
CS
5V
25
1624
23
17
26
19
20
1418 F25a
µP OR DSP
CLKOUT
INT
C0
SCK
MISO
t
5
t
6
12345678910111213141516
CS = 0, EXT/INT = 5
CONVST
EXTCLKIN
t
13
t
dEXTCLKIN
t
8
HOLD
SAMPLE
t
9
t
7
t
11
BUSY
SCLK
RD
12345678910111213141516 1234
1211109876543210
FILL
ZEROS
D13
Hi-Z
DATA N
Hi-Z
(SAMPLE N)
D
OUT
t
CONV
t
10
1418 F25b
D11D12
CAPTURE ON
RISING CLOCK
D13
t
15
t
14
SCLK
V
IL
V
OH
V
OL
D
OUT
CAPTURE ON
FALLING CLOCK
t
LSCLK
t
HSCLK
Figure 25. External Conversion Clock Selected. Data Transferred After Conversion
Using an External SCLK. BUSY↑ Indicates End of Conversion
Using External Conversion Clock and External Data
Clock. In Figure 25, data is also output after each conver-
sion is completed and before the next conversion is
started. An external clock is used for the conversion clock
and either another or the same external clock is used for
the SCLK. This mode is identical to Figure 24 except that
an external clock is used for the conversion. This mode