Datasheet

23
LTC1418
APPLICATIONS INFORMATION
WUU
U
clock and the SCLK. The internal clock has been optimized
for the fastest conversion time, consequently this mode
can provide the best overall speed performance. To select
an internal conversion clock, tie EXT/INT (Pin 20) low. The
internal clock appears on CLKOUT (Pin 18) which can be
tied to SCLK (Pin 17) to supply the SCLK.
Using External Clock for Conversion and Data Transfer.
In Figure 23, data from the previous conversion is output
during the conversion with an external clock providing
both the conversion clock and the shift clock. To select an
external conversion clock, tie EXT/INT high and apply the
Figure 23. External Conversion Clock Selected. Data Transferred During Conversion Using
the External Clock (External Clock Drives Both EXTCLKIN and SCLK)
serial port after transferring the serial output data by
tying it to the RD pin.
Figures 22 to 25 show several serial modes of operation,
demonstrating the flexibility of the LTC1418 serial port.
Serial Data Output During a Conversion
Using Internal Conversion Clock for Conversion and
Data Transfer. Figure 22 shows data from the previous
conversion being clocked out during the conversion with
the LTC1418 internal clock providing both the conversion
D12 D11
D11D12
CAPTURE ON
RISING CLOCK
D13
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
FILL
ZEROS
D13
1
t
5
t
6
t
10
2345678910111213141516 123
D13 D13 D12 D11
Hi-Z
Hi-Z
DATA NDATA (N – 1)
(SAMPLE N)
(SAMPLE N + 1)
D
OUT
CS = 0, EXT/INT = 5
EXTCLKIN (= SCLK)
CONVST
t
13
t
CONV
t
8
SAMPLE HOLDHOLD
t
dEXTCLKIN
t
7
t
11
1418 F23b
BUSY (= RD)
t
15
t
14
t
LEXTCLKIN
t
HEXTCLKIN
EXTCLKIN
(= SCLK)
V
IL
V
OH
V
OL
D
OUT
CAPTURE ON
FALLING CLOCK
LTC1418
BUSY (= RD)
EXTCLKIN ( = SCLK)
BUSYCONVSTCONVST
RD
EXTCLKIN
SCLK
EXT/INT
D
OUT
D
OUT
CS
5V
25
20
19
2624
17
16
23
1418 F23a
µP OR DSP