Datasheet

22
LTC1418
APPLICATIONS INFORMATION
WUU
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Figure 22. Internal Conversion Clock Selected. Data Transferred During Conversion Using
the ADC Clock Output as a Master Shift Clock (SCLK Driven from CLKOUT)
two zeros. The MSB (D13) will be valid on the first rising
and the first falling edge of the SCLK. D12 will be valid on
the second rising and the second falling edge as will all
the remaining bits. The data may be captured on either
edge. The largest hold time margin is achieved if data is
captured on the rising edge of SCLK.
BUSY gives the end of conversion indication. When the
LTC1418 is configured as a master serial device, BUSY
can be used as a framing pulse and to three-state the
t
15
t
14
SCLK
V
IL
V
OH
V
OL
D
OUT
1418 F21
Figure 21. SCLK to D
OUT
Delay
LTC1418
BUSY (= RD)
CLKOUT ( = SCLK)
BUSYCONVSTCONVST
RD
SCLK
CLKOUT
EXT/INT
D
OUT
2624
23
17
18
20
25
19
D
OUT
CS
1418 F22a
µP OR DSP
(CONFIGURED
AS SLAVE)
OR
SHIFT
REGISTER
D12 D11
D11D12
CAPTURE ON
RISING CLOCK
D13
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
FILL
ZEROS
D13
1
t
5
t
6
2345678910111213141516 123
D13 D13 D12 D11
Hi-Z
Hi-Z
DATA NDATA (N – 1)
(SAMPLE N)
(SAMPLE N + 1)
D
OUT
CS = EXT/INT = 0
CLKOUT (= SCLK)
CONVST
t
13
t
CONV
t
8
SAMPLE HOLDHOLD
t
10
t
7
t
11
1418 F22b
BUSY (= RD)
t
15
t
14
CLKOUT
(= SCLK)
V
IL
V
OH
V
OL
D
OUT
CAPTURE ON
FALLING CLOCK