Datasheet

LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
29
6957f
For more information www.linear.com/LTC6957-1
of 21°C to 26°C in the MS-12 package. For use to 125°C
ambient (H-grade) designers should be sure to check the
temperature rise using their specific output frequency,
loading, and supply voltages. The Absolute Maximum
rating for Junction Temperature is 150°C, which must be
avoided to prevent damaging the device, and as stated
in Note 1: "Exposure to any Absolute Maximum Rating
condition for extended periods of time may affect device
reliability and lifetime."
Low Phase Noise Design Considerations
Phase noise is a frequency domain representation of the
random variation in phase of a periodic signal. It is char-
acterized as the power at a given offset frequency relative
to the power of the fundamental frequency. Phase noise
is specified in dBc/Hz, decibels relative to the carrier in
a 1Hz bandwidth. It is essentially a frequency dependent
signal-to-noise ratio.
Designing for low phase noise is challenging, even with a
solid understanding of phase noise. Any designer attempt-
ing such a task will find a good working understanding of
what phase noise is, and how it behaves, to be the most
important tool to achieve success. One of the most intui-
tive explanations is found in Chapter 3, “
The Relationship
Between
Phase Jitter and Noise Density,” of W.P. Robins’
1982 text, “Phase Noise in Signal Sources.”
With a solid base of understanding, the designer will now
see that the entire clocking chain is full of potential phase
modulators. The noise of an amplifier is usually thought
of as an additive term, but for phase noise the bias noise,
to the extent that the amplifier bandwidth is dependent on
the bias level, is not an additive term but a modulating
term. The LTC6957 is a monolithic clock limiting ampli-
fier carefully designed so that users do not have to worry
about such details.
However, users of the LTC6957 still need to pay attention
to external considerations that can result in corruption of
the good phase noise performance available from all the
components used.
Timing jitter is a term used to describe the integration of
phase noise over a specified bandwidth which is presented
as a time domain specification.
Unfortunately, the term “low jitter” has become so over-
used that it is rendered virtually meaningless. High speed
communication links doing de-serialization and the like can
require jitter on the order of 30ps to 50ps. This is lower
jitter
than required for a clock on a micro-controller, but for
high
frequency sampling, even 1ps can severely impact the
dynamic range achievable. Therefore, it is best to ignore
the term “low jitter” and look for measured values of jitter,
and preferably phase noise. To analyze and measure true
low noise components, most instruments measure phase
noise (in dBc/Hz) rather than jitter.
A second consideration when designing for low phase
noise is that any clock signal is an analog signal and
should be thought of and routed as such. They should
not be run through large FPGAs with lots of activities at
multiple frequencies, they should not be routed through
PCB traces alongside digital data lines, and they should
not be routed through clock fan-out devices that have
features such as zero delay or programmable skew. The
specifics of the PCB traces and what surrounds them
should be analyzed as if the clock signals were among
your most sensitive analog signals, because in demanding
applications that is what your clock signals are. Note that
signal integrity software intended for analyzing crosstalk in
digital systems may only give yes or no answers and that
clocking performance can be compromised
at levels 40dB
to 60dB below what is required to get that “yes” answer.
Common pitfalls with clock signals are the same as for
sensitive analog signals: routing near or alongside digital
traces of any kind, crossing digital traces on an adjacent
layer within a sandwich of ground planes, using digital
power planes as part of layer sandwiches, and assuming
all of these are sufficiently mitigated by using differential
clock signaling.
The way to address these issues is also the same as for
sensitive analog signals: routing away from digital traces
wherever possible; routing with shielding of ground,
either planes, adjacent traces, or both; making realistic
assumptions of common mode rejections (30dB to 40dB
at most); and keeping a critical eye out for unintended
couplers during the design and debug phases.
Even if the world’s cleanest reference clock were used
to feed the LTC6957, simply routing it through a poorly
applicaTions inForMaTion