Datasheet

LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
19
6957f
For more information www.linear.com/LTC6957-1
applicaTions inForMaTion
General Considerations
The LTC6957-1/LTC6957-2/LTC6957-3/LTC6957-4 are
low noise, dual output clock buffers that are designed for
demanding, low phase noise applications. Properly applied,
they can preserve phase noise performance in situations
where alternative solutions would degrade the phase noise
significantly. They are also useful as logic converters.
However, no buffer device is capable of removing or
reducing phase noise present on an input signal. As with
most low phase noise circuits, improper application of
the LTC6957-1/LTC6957-2/LTC6957-3/LTC6957-4 can
result in an increase in the phase noise through a variety
of mechanisms. The information below will, hopefully,
allow a designer to avoid such an outcome.
The LTC6957 is designed to be used with high performance
clock signals destined for driving the encode inputs of
ADCs or mixer inputs. Such clocks should not be treated
as digital signals. The beauty of digital logic is that there
is noise margin both in the voltage and the timing, before
any deleterious effects are noticed. In contrast, high per-
formance clock signals have no margin for error in the
timing before the system performance is degraded. Us-
ers are encouraged to keep this distinction
in mind while
designing
the entire clocking signal chain before, during,
and after the LTC6957.
Input Interfacing
The input stage is the same for all versions of the LTC6957
and is designed for low noise and ease of interfacing to
sine-wave and small amplitude signals. Other logic types
can interface directly, or with little effort since they present
a smaller challenge for noise preservation.
Figure 1 shows a simplified schematic of the LTC6957
input stage. The diodes are all for protection, both during
ESD events and to protect the low noise NPN devices from
being damaged by input overdrive.
The resistors are to bias the input stage at an optimal
DC level, but they are too large to leave floating without
increasing the noise. Therefore, for low noise use, always
connect both inputs to a low AC impedance. A capacitor
to ground/return is imperative on the unused input in
single-ended applications.
Figure 2a shows how to interface single-ended LVPECL
logic to the LTC6957, while Figure 2b shows how to drive
the LTC6957 with differential LVPECL signals. The capaci-
tors shown are 10nF and can be inexpensive ceramics,
preferably in small SMT cases. For use above 100
MHz,
lower
value capacitors may be desired to avoid series
resonance, which could increase the noise in Figure 2a
even though the capacitor is just on the DC input. This
comment applies to all capacitors hooked to the inputs
throughout this data sheet.
In Figure 2a, the R
TERM
implementation is up to the user
and is to terminate the transmission line. If it is connected
to a V
TT
that is passively generated and heavily bypassed
to ground, the 10nF to ground shown on the inverting
LTC6957 input is the appropriate connection to use.
However, if the termination goes to an actively generated
V
TT
voltage, lower noise may be achieved by connecting
the capacitor on the inverting input to that V
TT
rather than
ground.
In Figure 2b, both inputs to the LTC6957 are driven, in-
creasing the differential input signal size and minimizing
noise from any common mode source such as V
TT
, both
of which improve the achievable phase noise.
A variety of termination techniques can be used, and
as long as the two sides use the same termination, the
configuration used won't matter much. In Figure 2b, the
Figure 1
6957 F01
FILTA
FILTB
IN
+
IN
–
V
+
GND
1.8k
3.2k
2mA
1.2k
1.2k
1
6
3
4
2
FILTERS
5