Datasheet

LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
16
6957f
For more information www.linear.com/LTC6957-1
pin FuncTions
FILTA, FILTB (Pin 1, Pin 6): Input Bandwidth Limiting
Control. These CMOS logic inputs control the bandwidth
of the early amplifier stages. For slow slewing signals
substantially lower phase noise is achieved by using this
feature. See the Applications Information section for more
details.
V
+
(Pin 2): Supply Voltage (3.15V to 3.45V). This sup-
ply must be kept free from noise and ripple. It should be
bypassed directly to GND (Pin 5) with a 0.1µF capacitor.
IN
+
, IN
–
(Pin 3, Pin 4): Input Signal Pins. These inputs
are differential, but can also interface with single-ended
signals. The input can be a sine wave signal or a CML,
LVPECL, TTL or CMOS logic signal. See the Applications
Information section for more details.
GND (Pin 5): Ground. Connect to a low inductance ground
plane for best performance. The connection to the bypass
capacitor for V
+
(Pin 2) should be through a direct, low
inductance path.
SD1, SD2 (Pin 12, Pin 7): Output Enable Control. These
CMOS logic inputs control the enabling and disabling of
their respective OUT1 and OUT2 outputs. When both out-
puts are disabled, the LTC6957 is placed in a low power
shutdown state.
LTC6957-1 Only
OUT1
–
, OUT1
+
(Pin 10, Pin 11): LVPECL Outputs. Differential
logic outputs typically terminated by 50Ω connected to a
supply 2V below the V
+
supply. Refer to the Applications
Information section for more details.
OUT2
–
, OUT2
+
(Pin 9, Pin 8): LVPECL Outputs. Differential
logic outputs typically terminated by 50Ω connected to a
supply 2V below the V
+
supply. Refer to the Applications
Information section for more details.
LTC6957-2 Only
OUT1
–
, OUT1
+
(Pin 10, Pin 11): LVDS Outputs, Mostly
TIA/EIA-644-A Compliant. Refer to the Applications Infor-
mation section for more details.
OUT2
–
, OUT2
+
(Pin 9, Pin 8): LVDS Outputs, Mostly TIA/
EIA-644-A Compliant. Refer to the Applications Information
section for more details.
LTC6957-3/LTC6957-4 Only
OUT1, OUT2 (Pin 10, Pin 9): CMOS Outputs. Refer to the
Applications Information section for more details.
V
DD
(Pin 11): Output Supply Voltage (2.4V to 3.45V). For
best performance connect this to the same supply as V
+
(Pin 2). If the output needs to be a lower logic rail, this
supply can be separately connected, but this voltage must
be less than or equal to that on Pin 2 for proper operation.
This supply must also be kept free from noise and ripple.
It should be bypassed directly to
the GNDOUT pin (Pin 8)
with a 0.1µF capacitor.
GNDOUT
(Pin 8): Output Logic Ground. Tie to a low
inductance ground plane for best performance. The con-
nection to the bypass capacitor for V
DD
(Pin 11) should
be through a direct, low inductance path.
LTC6957-xDD Only
Exposed Pad (Pin 13): Always tie the underlying DFN
exposed pad to GND (Pin 5). To achieve the rated θ
JA
of
the DD package, there should be good thermal contact
to the PCB.