Datasheet

LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
28
6957f
For more information www.linear.com/LTC6957-1
CMOS Outputs of the LTC6957-3/LTC6957-4
Figure 11 shows a simplified schematic of the LTC6957-3/
LTC6957-4 CMOS output stage. The LTC6957-3 outputs
are driven synchronously in-phase, while the LTC6957-4
outputs are driven differentially out-of-phase.
Although the LTC6957-3/LTC6957-4 are specified for a
resistive load, the outputs can drive capacitive loads as
well. With more than a few picoFarads of load, the rise
and fall times will be degraded in direct proportion to the
load capacitance.
During shutdown, the LTC6957-3 outputs will both be
set to a logic low.
During shutdown, the LTC6957-4 OUT1 will be set to a
logic low, while OUT2 will be set to a logic high.
During transitions to and from shutdown, the LTC6967-3/
LTC6957-4 outputs may not comply with the specified
output levels for any length of time after the rising edge
of SD1/SD2, nor for any time before sufficient t
WAKEUP
/
t
ENABLE
subsequent to the falling edge of SD1/SD2. The
applicaTions inForMaTion
outputs may have one or two errant transitions resulting
in runt pulses being seen. The LTC6957-3/LTC6957-4
shutdown capability should be used as a slow, power-
saving on/off control,
not a logic gating/enable control, and
because they can not be put in a high impedance (3-state)
condition, the shutdown functionality is not usable as a
way to multiplex multiple outputs or devices.
Power Supplies for CMOS Operation
The LTC6957-3/LTC6957-4 operate with V
+
from 3.15V
to 3.45V only. If the LTC6957-3/LTC6957-4 are used to
drive CMOS logic at a lower voltage rail, the output stage
can be powered (Pin 11) by a lower voltage, down to
2.4V
MIN
. Note that significant degradation of the spectral
purity could occur if the output supply, V
DD
, is not clean,
either because of additional broadband noise or discrete
spectral tones. The nature of a CMOS logic gate forms an
AM modulator of low frequency disturbances on the power/
ground that modulate the signal propagating through the
CMOS gate. Numerous common phenomena can serve
to convert the AM to PM/FM and, even if the conversion
efficiency is low, corrupt the phase noise to unacceptable
levels in demanding applications.
If two separate supplies are used, the only supply sequenc-
ing issue to be aware of is that if the V
DD
comes up first,
the OUT1/OUT2 CMOS outputs will be high impedance
until
V
+
> ~1V. Note that the four CMOS control inputs are
all referenced to V
+
, not the output supply. Also note that
during operation the output supply should be equal to or
less than V
+
. The LTC6957-3/LTC6957-4 will function with
V
DD
several hundred millivolts above the V
+
supply, but
depending on the load, this margin for error can largely
be consumed by transient load steps.
When driving capacitive loads at high frequencies, the
LTC6957-3/LTC6957-4 V
DD
power consumption can jump
considerably over the quiescent power taken from V
+
. The
Dynamic current specification is with no load and adds
directly to the current needed to repetitively charge and
discharge a capacitive load.
With 24mA drawn from V
+
at 3.3V, and another 20mA
to 30mA drawn from V
DD
(easy to do with two outputs
active at 300MHz), the total power consumption can be
145mW to 178mW, resulting in a junction-to-ambient rise
Figure 11. LTC6957-3/LTC6957-4 CMOS Outputs
6957 F11
OUT1
V
DD
GND
OUT
OUT2
LTC6957-3/LTC6957-4