Datasheet

ManualsBrandsLINEAR TECHNOLOGY ManualsDev KitsPCB design board

LTC6957-1/LTC6957-2/

LTC6957-3/LTC6957-4

6957f

For more information www.linear.com/LTC6957-1

Typical applicaTion

FeaTures DescripTion

Low Phase Noise, Dual

Output Buffer/Driver/

Logic Converter

The LT C

6957-1/LTC6957-2/LTC6957-3/LTC6957-4 is

a family of very low phase noise, dual output AC signal

buffer/driver/logic level translators. The input signal can

be a sine wave or any logic level (≤2V

P-P

). There are four

members of the family that differ in their output logic

signal type as follows:

LTC6957-1: LVPECL Logic Outputs

LTC6957-2: LVDS Logic Outputs

LTC6957-3: CMOS Logic, In-Phase Outputs

LTC6957-4: CMOS Logic, Complementary Outputs

The LTC6957 will buffer and distribute any logic signal

with minimal additive noise, however, the part really ex-

cels at translating sine wave signals to logic levels. The

early amplifier stages have selectable lowpass filtering

to minimize the noise while still amplifying the signal to

increase its slew rate. This input stage filtering/noise limit-

ing is especially helpful in delivering the lowest possible

phase noise signal with slow slewing input signals such

as a typical 10MHz sine wave system reference.

L, LT , LT C, LT M, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Protected by U.S. Patents 7969189 and 8319551.

Additive Phase Noise at 100MHz

applicaTions

Low Phase Noise Buffer/Driver

Optimized Conversion of Sine Wave Signals to

Logic Levels

Three Logic Output Types Available

– LVPECL

– LVDS

– CMOS

Additive Jitter 45fs

RMS

(LTC6957-1)

Frequency Range Up to 300MHz

3.15V to 3.45V Supply Operation

Low Skew 3ps Typical

Fully Specified from –40°C to 125°C

12-Lead MSOP and 3mm × 3mm DFN Packages

System Reference Frequency Distribution

High Speed ADC, DAC, DDS Clock Driver

Military and Secure Radio

Low Noise Timing Trigger

Broadband Wireless Transceiver

High Speed Data Acquisition

Medical Imaging

Test and Measurement

OFFSET FREQUENCY (Hz)

100

–165

PHASE NOISE (dBc/Hz)

–160

–155

–150

–140

1k 10k 100k

69571234 TA01b

–145

LTC6957-1 (LVPECL)

LTC6957-4 (CMOS)

LTC6957-3

(CMOS)

LTC6957-2 (LVDS)

SINGLE-ENDED SINE WAVE INPUT

AT +7dBm (500mV

RMS

)

FILTA = FILTB = GND

6957 TA01a

SD1

SD2

GND

OUT2

OUT1

FILTA

FILTB

10nF

50Ω

100MHz

+7dBm

SINE WAVE

10nF

–

OCXO

3.3V

TO PLL CHIPS

OR SYSTEM

SAMPLING CLOCKS

0.1µF

Summary of content (36 pages)

PAGE 1
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Low Phase Noise, Dual Output Buffer/Driver/ Logic Converter Description Features Low Phase Noise Buffer/Driver n Optimized Conversion of Sine Wave Signals to Logic Levels n Three Logic Output Types Available – LVPECL – LVDS – CMOS n Additive Jitter 45fs RMS (LTC6957-1) n Frequency Range Up to 300MHz n 3.15V to 3.
PAGE 2
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Absolute Maximum Ratings (Note 1) Supply Voltage (V+ or VDD) to GND...........................3.6V Input Current (IN+, IN–, FILTA, FILTB, SD1, SD2) (Note 2)........................................................... ±10mA LTC6957-1 Output Current ......................... 1mA, –30mA LTC6957-2 Output Current .................................. ±10mA LTC6957-3, LTC6957-4 Output Current (Note 3)... ±30mA Specified Temperature Range LTC6957I............................
PAGE 3
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LTC6957IDD-1#PBF LTC6957IDD-1#TRPBF LFQJ 12-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LTC6957IDD-2#PBF LTC6957IDD-2#TRPBF LFQK 12-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LTC6957IDD-3#PBF LTC6957IDD-3#TRPBF LFQM 12-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LTC6957IDD-4#PBF LTC6957IDD-4#TRPBF LFQN 12-Lead (3mm × 3mm) Plastic DFN –4
PAGE 4
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Electrical Characteristics LTC6957-1 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3.3V, SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, RLOAD = 50Ω connected to 1.3V, unless otherwise specified. All voltages are with respect to ground. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 300 MHz 0.8 2 VP-P 0.
PAGE 5
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Electrical Characteristics LTC6957-1 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3.3V, SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, RLOAD = 50Ω connected to 1.3V, unless otherwise specified. All voltages are with respect to ground.
PAGE 6
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Electrical Characteristics LTC6957-2 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3.3V, SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, RLOAD = 110Ω differential, unless otherwise specified. All voltages are with respect to ground.
PAGE 7
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Electrical Characteristics LTC6957-2 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3.3V, SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, RLOAD = 110Ω differential, unless otherwise specified. All voltages are with respect to ground.
PAGE 8
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Electrical Characteristics LTC6957-3/LTC6957-4 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = VDD = 3.3V, SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, RLOAD = 480Ω to VDD /2, unless otherwise specified. All voltages are with respect to ground.
PAGE 9
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Electrical Characteristics LTC6957-3/LTC6957-4 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = VDD = 3.3V, SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, RLOAD = 480Ω to VDD /2, unless otherwise specified. All voltages are with respect to ground.
PAGE 10
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Typical Performance Characteristics Input Self Bias Voltage vs Temperature Supply Current vs Supply Voltage 20 V+ = 3.45V 16 2.10 SUPPLY CURRENT (mA) INPUT VOLTAGE (V) NO OUTPUT LOADS 18 2.15 V+ = 3.3V 2.05 2.00 V+ = 3.15V 18.4 12 TA = –55°C TA = 25°C 10 8 6 5 25 45 65 85 105 125 TEMPERATURE (°C) 17.2 16.8 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V) 2.45 Supply Current vs Temperature 58 V+ = 3.3V 50Ω LOADS TO 1.3V 1.
PAGE 11
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Typical Performance Characteristics Additive Phase Noise vs Input Frequency 300MHz 153.6MHz –155 –160 –140 –10dBm, FILTA = L, FILTB = H –145 0dBm, FILTA = H, FILTB = L –150 –155 –165 100 1M 1k 10k 100k OFFSET FREQUENCY (Hz) 69571234 G10 PHASE NOISE (dBc/Hz) –150 3.45V 3.3V –160 –145 0dBm, FILTA = H, FILTB = L –150 –155 7dBm, FILTA = FILTB = L –165 1k 10k 100k 100 OFFSET FREQUENCY (Hz) 1M 0.550 3.
PAGE 12
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Typical Performance Characteristics Input Self Bias Voltage vs Temperature Supply Current vs Supply Voltage V+ = 3.45V 40 V+ = 3.3V 2.05 2.00 V+ = 3.15V 40.5 35 SUPPLY CURRENT (mA) 30 TA = 125°C 25 20 TA = 25°C 15 TA = –55°C 10 1.95 0 5 25 45 65 85 105 125 TEMPERATURE (°C) DC DATA, IN+ > (IN– + 50mV) VOH, VOL AND VOS (V) 1.0 0 50 410 1.2 VOD (CALCULATED) 400 250 1.0 –55 –35 –15 1.0V 1.5V 3.0V 0V SD OUT– 1.
PAGE 13
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Typical Performance Characteristics –140 –145 153.6MHz –150 300MHz –155 –160 –135 PHASE NOISE (dBc/Hz) –135 PHASE NOISE (dBc/Hz) –130 SINGLE-ENDED SINE WAVE INPUT AT 7dBm (500mVRMS) FILTA = FILTB = L –165 100 –10dBm, FILTA = L, FILTB = H –145 0dBm, FILTA = H, FILTB = L –150 1k 10k 100k OFFSET FREQUENCY (Hz) –155 PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz) 3.45V –150 3.3V –155 3.
PAGE 14
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Typical Performance Characteristics Input Self Bias Voltage vs Temperature Supply Current vs Supply Voltage V+ = 3.45V V+ SUPPLY CURRENT (mA) V+ = 3.3V 2.05 2.00 V+ = 3.15V 20 15 25°C 10 125°C 5 1.95 0 5 25 45 65 85 105 125 TEMPERATURE (°C) 0.6 0 2.4 1.2 1.8 V+ VOLTAGE (V) 3 69571234 G37 V+ = 3.15V 20.0 0.25 0 5 10 15 LOAD CURRENT (mA) 125°C VDD – 0.75 VDD = 3.3V 0.50 OUTPUT LOW, SINKING CURRENT 0.
PAGE 15
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Typical Performance Characteristics –140 300MHz –145 153.6MHz –150 –155 –135 PHASE NOISE (dBc/Hz) –135 PHASE NOISE (dBc/Hz) –130 SINGLE-ENDED SINE WAVE INPUT AT 7dBm (500mVRMS) FILTA = FILTB = L 100MHz –10dBm, FILTA = L, FILTB = H –145 0dBm, FILTA = H, FILTB = L –150 –155 –165 100 –165 100 SINGLE-ENDED SINE WAVE INPUT, 100MHz AT 7dBm (500mVRMS) V+ = VDD FILTA = FILTB = L 3.15V 3.
PAGE 16
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Pin Functions FILTA, FILTB (Pin 1, Pin 6): Input Bandwidth Limiting Control. These CMOS logic inputs control the bandwidth of the early amplifier stages. For slow slewing signals substantially lower phase noise is achieved by using this feature. See the Applications Information section for more details. V+ (Pin 2): Supply Voltage (3.15V to 3.45V). This supply must be kept free from noise and ripple. It should be bypassed directly to GND (Pin 5) with a 0.
PAGE 17
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Block Diagrams 1 6 3 4 FILTA 2 12 V+ SD1 OUT1+ FILTB OUT1– IN+ 11 10 IN– OUT2– OUT2+ 5 GND 9 8 SD2 7 LTC6957-1 and LTC6957-2 1 6 3 4 FILTA 2 V+ 12 SD1 FILTB V DD OUT1 11 10 IN+ IN– OUT2 9 GNDOUT 8 5 GND 7 SD2 6957 BD LTC6957-3 and LTC6957-4 6957f For more information www.linear.
PAGE 18
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Timing Diagram SD1 SD2 INPUT OUT1+/OUT1 OUT1– OUT2+/OUT2 OUT2– tDISABLE tSLEEP tWAKEUP tENABLE DETAIL INPUT SEE APPLICATIONS INFORMATION FOR LOGIC BEHAVIOR DURING SHUTDOWN SPECIFIC TO LVPECL/LVDS/CMOS tPD 50% OUT1+/OUT1 OUT1– 50% tMATCH 90% OUT2+/OUT2 OUT2– 10% tRISE 90% 6957 TD1 10% tFALL tSKEW 6957f 18 For more information www.linear.
PAGE 19
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Applications Information General Considerations 2 The LTC6957-1/LTC6957-2/LTC6957-3/LTC6957-4 are low noise, dual output clock buffers that are designed for demanding, low phase noise applications. Properly applied, they can preserve phase noise performance in situations where alternative solutions would degrade the phase noise significantly. They are also useful as logic converters.
PAGE 20
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Applications Information RTERMs are shown in a "Y" configuration that creates a passive VTT at the common point. Most 3.3V LVPECL devices have differential outputs and can be terminated with three 50Ω resistors as shown. Figure 3 shows a 50Ω RF signal source interface to the LTC6957. For a pure tone (sine wave) input, Figure 3 can handle up to 10dBm maximum.
PAGE 21
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Applications Information Figure 5 shows the LTC6957 being driven by an LVDS (EIA-644-A) signal pair. This is simply a matter of differentially terminating the pair and AC-coupling as shown into the LTC6957 whose DC common mode voltage is incompatible with the LVDS standard. The choice of 110Ω versus 100Ω termination is arbitrary (the EIA-644-A standard allows 90Ω to 132Ω) and should be made to match the differential impedance of the trace pair.
PAGE 22
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Applications Information Figure 6 shows a suggested CMOS to LTC6957 interface. The transmission line shown is the PCB trace and the component values are for a characteristic impedance of 50Ω, though they could be scaled up or down for other values of Z0. The R1/R2 divider at the CMOS output cuts the Thevenin voltage in half when the ZOUT of the driver is included.
PAGE 23
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Applications Information Table 2 has the slew rate ranges most suitable for the four different filter settings. Table 2 FILTA FILTB INPUT SLEW RATE (V/µs) Low Low >400 High Low 125 to 400 Low High 40 to 125 High High <40 With +10dBm at 100MHz, the input slew rate is 628V/µs and Table 2 indicates the best filter setting to use is FILTA = FILTB = L, which is seen to be the case in Figure 7a.
PAGE 24
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Applications Information Evidently, the input filtering will not significantly help with large and fast slewing input signals to the LTC6957. As seen in Figure 1, the input has a differential pair before the filters, so the limiting will already have happened before the filter. Fortunately, with large input signals, performance is typically better than with smaller input signals because phase noise is a signal-to-noise phenomenon.
PAGE 25
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Applications Information This data is shown for the LTC6957-2, but the effect is due to the input stage that is common to all versions, so any other version will have the same general behavior. The LTC6957-3 and LTC6957-4 CMOS outputs may have additional tPD+ vs tPD– discrepancies due to differences between the NMOS and PMOS output devices, particularly when driving heavy loads.
PAGE 26
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Applications Information During transitions to and from shutdown, the LTC6957-1 outputs are not guaranteed to comply with the specified output levels for any length of time after the rising edge of SD1/SD2, nor for any time before sufficient tWAKEUP / t ENABLE subsequent to the falling edge of SD1/SD2. The output common mode and differential voltage could have a slow settling time compared to the signal frequency, and a long string of runt pulses could be seen.
PAGE 27
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Applications Information LVDS Outputs of the LTC6957-2 Figure 10 shows a simplified schematic of the LTC6957-2 LVDS output stage. The TIA/EIA-644-A standard specifies the generator electrical requirements for this type of interface, and the LTC6957-2 has been verified against that standard using the following test methods: SPECIFICATION LEVEL OF TESTING 4.1.1 100% Production Tested 4.1.2 100% Production Tested 4.1.3 100% Production Tested 4.1.
PAGE 28
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Applications Information CMOS Outputs of the LTC6957-3/LTC6957-4 Figure 11 shows a simplified schematic of the LTC6957-3/ LTC6957-4 CMOS output stage. The LTC6957-3 outputs are driven synchronously in-phase, while the LTC6957-4 outputs are driven differentially out-of-phase. Although the LTC6957-3/LTC6957-4 are specified for a resistive load, the outputs can drive capacitive loads as well.
PAGE 29
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Applications Information of 21°C to 26°C in the MS-12 package. For use to 125°C ambient (H-grade) designers should be sure to check the temperature rise using their specific output frequency, loading, and supply voltages.
PAGE 30
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Applications Information designed system would result in compromised spectral performance. This often catches designers by surprise because the mechanisms above are typically additive and linear, which result in filtering and additional spectral components, but don’t by themselves create phase modulation. Unfortunately, any limiter, including the LTC6957, will, through its nonlinear action, transform additive terms into phase modulation.
PAGE 31
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Applications Information 50Ω TERMINATION 2V MINI-CIRCUITS ZHL-2010+ –1.3V DUT N5500A REF 1 AGILENT 8644 122.88MHz 12.
PAGE 32
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Applications Information 50Ω load to ground directly, but this creates a DC offset (the signal is always positive) that the amplifier cannot take, so a bias tee was included in the DUT signal path. Only the 122.88MHz sine wave will be in the path without the DUT, going to the N5500A signal port, until the first coupler. This coupler allows a spur input to be injected, while a second coupler allows the size of the spur, relative to the carrier, to be measured.
PAGE 33
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Typical Applications Crystal Oscillator 5VIN+ LT1761-3.3V OUT BP 0.01µF 3.3V 10µF 1µF TO ALL V+ POINTS 0.1µF V+ 2 50MHz + V BANDWIDTH 1 V+ 6 SD1 VDD FILTB OUT1 0.1µF 11 10 IN+ 3 30pF 12 V+ FILTA IN– 4 OUT2 2k GNDOUT LTC6957-3 5 GND 7 450Ω 9 8 OUT TO 50Ω 0.
PAGE 34
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. DD12 Package 12-Lead (3mm × 3mm) Plastic DFN (Reference LTC DWG # 05-08-1725 Rev A) 0.70 ±0.05 3.50 ±0.05 2.10 ±0.05 2.38 ±0.05 1.65 ±0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.45 BSC 2.25 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 3.00 ±0.10 (4 SIDES) R = 0.115 TYP 7 0.40 ± 0.10 12 2.38 ±0.
PAGE 35
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MS Package 12-Lead Plastic MSOP (Reference LTC DWG # 05-08-1668 Rev Ø) 0.889 ±0.127 (.035 ±.005) 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 4.039 ±0.102 (.159 ±.004) (NOTE 3) 0.65 (.0256) BSC 0.42 ±0.038 (.0165 ±.0015) TYP 12 11 10 9 8 7 RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) DETAIL “A” 3.00 ±0.102 (.118 ±.004) (NOTE 4) 4.90 ±0.152 (.
PAGE 36
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Typical Application 10MHz Frequency Reference Input Stage with Dual CMOS Outputs Additive Phase Noise vs Input Amplitude 3.3V 0.1µF 0.1µF LTC6957-3 FILTA 0.1µF 10MHz REF IN –10dBm to 24dBm COILCRAFT WBC16-1T • R1 100Ω HSMS-281C 0.1µF • 0.1µF R2 604k 1 FILTB R1 100Ω SD1OUT V+ 3 IN+ OUT1 4 IN– OUT2 5 0.