Datasheet

LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
26
6957f
For more information www.linear.com/LTC6957-1
During transitions to and from shutdown, the LTC6957-1
outputs are not guaranteed to comply with the specified
output levels for any length of time after the rising edge
of SD1/SD2, nor for any time before sufficient t
WAKEUP
/
t
ENABLE
subsequent to the falling edge of SD1/SD2. The
output common mode and differential voltage could have
a slow settling time compared to the signal frequency, and
a long string of runt pulses could be seen. The LTC6957-1
shutdown capability should be used as a slow on/off
control, not a logic gating/enable control.
Power Supplies for LVPECL Operation
The LTC6957-1 can operate from 3.15V to 3.45V total
supply voltage difference, irrespective of the absolute
level of those voltages. The convention in LVPECL is that
the negative supply is ground, while in ECL the positive
supply may be ground or 2.0V. The LTC6957-1 can work
in all of these situations provided the total supply voltage
difference is within the 3.15V to 3.45V range. No special
supply sequencing will be needed. With a 2V rail the out-
put terminations go to ground, while, with the positive
supply grounded, the outputs can tolerate short circuits
to ground. However
, the four CMOS logic input signals
will
need to be driven with respect to whatever absolute
levels of supply voltages are used. If FILTA, FILTB, SD1,
and SD2 are fixed, they can be tied to the appropriate rail
and this is not a problem. Interface logic levels could get
tricky if they need to be programmed in-system.
In any voltage configuration, be aware that the LVPECL
output stage depends on the external load to complete its
biasing and, as such, is susceptible to phase modulation
as the supply voltage changes. The LTC6957-1 is gener-
ally less sensitive to variations in the supply voltage if the
termination voltage tracks the supply rather than ground.
With all four outputs terminated or otherwise driving heavy
loads, the LTC6957-1 power consumption and temperature
rise may be an issue.
Fortunately, the data sheet specification for supply cur-
rent with output loads does not need to be multiplied
by the entire supply voltage to calculate on-chip power
dissipation because most of that current flows through
the loads which will dissipate a significant portion of the
total system power.
Typically, the internal power consumption will be (20mA •
3.3V = ) 66mW, while the on-chip
power dissipation
from
the output loading will be less than half that number. With a
total power dissipation on-chip of 90mW, the temperature
rise in the MS-12 package will be 13°C given the θ
JA
of that
package. For use to 125°C ambient (H-grade) designers
should be sure to check the temperature rise using their
specific output loading and supply levels. The Absolute
Maximum rating for Junction Temperature is 150°C, and
must be avoided to prevent damaging the device, and as
stated in Note 1: "Exposure to any Absolute Maximum
Rating condition for extended periods of time may affect
device reliability and lifetime."
applicaTions inForMaTion