Datasheet

LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
21
6957f
For more information www.linear.com/LTC6957-1
applicaTions inForMaTion
Figure 5 shows the LTC6957 being driven by an LVDS
(EIA-644-A) signal pair. This is simply a matter of differ-
entially terminating the pair and AC-coupling as shown
into the LTC6957 whose DC common mode voltage is
incompatible with the LVDS standard.
The choice of 110Ω versus 100Ω termination is arbitrary
(the EIA-644-A standard allows 90Ω to 132Ω) and should
be made to match the differential impedance of the trace
pair. The termination and AC-coupling elements should
be located as close as possible to the LTC6957.
If DC-coupling is desired, for example to control the
LTC6957 output phasing during times the LVDS input
clocks will be halted, a pair of 3k resistors can parallel the
two capacitors in Figure 5. An EIA/TIA-644-A compliant
driver can drive this load, which is less load stress than
specification 4.1.1. The differential voltage into the LTC6957
when clocked (>100kHz) will be full LVDS levels. When
the clocks stop, the DC differential voltage created by the
resistors and the 1.2k internal resistors (Figure 1) will
be 100mV, still sufficient to assure the desired LTC6957
output polarity. Choosing the smallest capacitors needed
for phase noise
performance will minimize the settling
transients when the clocks restart.
Interfacing with CMOS Logic
The logic families discussed and illustrated to this point are
generally a better choice for routing and distributing low
phase-noise reference/clock signals than is CMOS logic.
All of the logic types shown so far are well suited for use
with low impedance terminations. Most of the time there
is a differential signal when using LVPECL or CML, and
LVDS always has a differential signal. Differential signals
provide lots of margin for error when it comes to picking up
noise and interference that can corrupt a reference clock.
CMOS on the other hand cannot drive 50Ω loads, is usually
routed single-ended, and by its nature is coupled to the
potentially noisy supply voltage half the time.
The LTC6957-3/LTC6957-4 provide CMOS outputs, so it
may seem surprising to read herein that CMOS is a poor
choice for low phase noise applications. However, these
devices should prove useful for designers that recognize
the challenges and limitations of using CMOS signals for
low phase noise applications. See the CMOS Outputs of
the LTC6957-3/LTC6957-4 section for further information.
The best method for driving the
LTC6957 with
CMOS
signals would be to provide differential drive, but if that
is not available, there are few ways to create a differential
CMOS signal without running the risk of corrupting the
skew or creating other problems. Therefore, single-ended
CMOS signals are the norm and care must be taken when
using this to drive the LTC6957.
The primary concern is that all routing should be termi-
nated to minimize reflections. With CMOS logic there is
usually plenty of signal (more than the LTC6957 can handle
without attenuation) and the amplitude of the LTC6957
input signal will generally be of secondary importance
compared to avoiding the deleterious effects of signal
reflections. The primary concern about terminations is
that the input waveform presented to the LTC6957 should
have full speed slewing at the all important transitions.
If a rising edge is slowed by the destructive addition of
the ringing/settling of a prior edge reflection, or even the
start of the current edge, the phase noise performance will
suffer. This is true for all logic types, but is particularly
problematic when using CMOS because of the fast slew
rates and because it does not naturally lend itself to
clean
terminations.
Point-to-point routing is best, and care should be taken to
avoid daisy-chain routing, because the terminated end may
be the only point along the line that sees clean transitions.
Earlier loads may even see a dwell in the transition region
which will greatly degrade phase noise performance.
Figure 5. LVDS Input
6957 F05
110Ω
–
+
LTC6957
10nF
10nF