Datasheet

LTM4620A
23
4620afb
For more information www.linear.com/LTM4620A
Figure 9. Graphical Representation of JESD51-12 Thermal Coefficients
4620A F10
µMODULE DEVICE
JUNCTION-TO-CASE (TOP)
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
CASE (TOP)-TO-AMBIENT
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
JUNCTION
AMBIENT
CASE (BOTTOM)-TO-BOARD
RESISTANCE
Within a SIP (system-in-package) module, be aware there
are multiple power devices and components dissipating
power, with a consequence that the thermal resistances
relative to different junctions of components or die are not
exactly linear with respect to total package power loss. To
reconcile this complication without sacrificing modeling
simplicity—but also, not ignoring practical realities—an
approach has been taken using FEA software modeling
along with laboratory testing in a controlled-environment
chamber to reasonably define and correlate the thermal
resistance values supplied in this data sheet: (1) Initially,
FEA software is used to accurately build the mechanical
geometry of the µModule and the specified PCB with all
of the correct material coefficients along with accurate
power loss source definitions; (2) this model simulates
a software-defined JEDEC environment consistent with
JSED51-9 to predict power loss heat flow and temperature
readings at different interfaces that enable the calculation of
the JEDEC-defined thermal resistance values; (3) the model
and FEA software is used to evaluate the µModule with
heat sink and airflow; (4) having solved for and analyzed
these thermal resistance values and simulated various
operating conditions in the software model, a thorough
laboratory evaluation replicates the simulated conditions
with thermocouples
within a controlled-environment
chamber
while operating the device at the same power loss
as that which was simulated. An outcome of this process
and due-diligence yields a set of derating curves provided
in other sections of this data sheet. After these laboratory
test have been performed and correlated to the µModule
model, then the θ
JB
and θ
BA
are summed together to cor-
relate quite well with the µModule model with no airflow or
heat
sinking in a properly define chamber. This θ
JB
+ θ
BA
value is shown in the Pin Configuration section and should
accurately equal the θ
JA
value because approximately
100% of power loss flows from the junction through the
board into ambient with no airflow or top mounted heat
sink. Each system has its own thermal characteristics,
therefore thermal analysis must be performed by the user
in a particular system.
APPLICATIONS INFORMATION