Datasheet

LTC4417
17
4417f
applicaTions inForMaTion
P-channel’s gate to source voltage when driving the load
and inrush current, C
S
is the slew rate capacitor and C
L
is the V
OUT
hold up capacitance. The output load current
I
L
is neglected for simplicity. Choose C
S
to be at least ten
times the external P-channel MOSFET’s C
RSS(MAX)
, and
C
VS
to be ten times C
S
.
R
S
≥
ΔV
G(SINK)
– V
GS
( )
• C
L
•R
SRC
C
S
• V1
DROOP
(16)
Use Equation (17) to verify the inrush current limit is lower
than the absolute maximum pulsed drain current, I
DM
.
I
INRUSH
=
V1
DROOP
R
SRC
(17)
If the external P-channel MOSFET’s reverse transfer
capacitance, C
RSS
, is used instead of C
S
, replace C
S
with
C
RSS
in Equation (16), where C
RSS
is taken at the minimum
V
DS
voltage, and calculate for R
S
. Depending on the size
of C
RSS
, R
S
may be large. Care should be used to ensure
gate leakages do not inadvertently turn off the channel over
temperature. This is particularly true of built in Zener gate-
source protected devices. Careful bench characterization
is strongly recommended, as C
RSS
is non-linear.
The preceding analysis assumes a small input inductance
between the input supply voltage and the drain of the ex-
ternal P-channel MOSFET. If the input inductance is large,
choose C
V1
to be much greater than C
L
and replace R
SRC
with the ESR of C
V1
.
When slew rate limiting the output, ensure power dis-
sipation does not exceed the manufacturer’s SOA for the
chosen external P-channel MOSFET. Refer to the Selecting
External P-channel MOSFETs section.
TRANSIENT SUPPLY PROTECTION
The LTC4417’s abrupt switching due to OV or UV faults
can create large transient overvoltage events with inductive
input supplies, such as supplies connected
by a long cable
.
At times the transient overvoltage condition can exceed
twice the nominal voltage. Such events can damage external
devices and the LTC4417. It is imperative that external
back-to-back P-channel MOSFET devices do not exceed
their single pulse avalanche energy specification (EAS) in
unclamped inductive applications and input voltages to the
LTC4417 never exceed the Absolute Maximum Ratings.
To minimize inductive voltage spikes, use wider and/or
heavier trace plating. Adding a snubber circuit will dampen
input voltage spikes as discussed in Linear Application
Note 88, and a transient surge suppressor at the input will
clamp the voltage. Transient voltage suppressors (TVS)
should be placed on any input supply pin, V1, V2 and V3,
where input shorts, or reverse voltage connection can be
made. If short-circuit of input sources powering V
OUT
are
possible, transient voltage suppressors should also be
placed on V
OUT
, as shown in Figure 9.
When selecting transient voltage suppressors, ensure the
reverse standoff voltage (V
R
) is equal to or greater than
the application operating voltage, the peak pulse current
(I
PP
) is higher than the peak transient voltage divided by
the source impedance, the maximum clamping voltage
(V
CLAMP
) at the rated I
PP
is less than the absolute maxi-
mum ratings of the LTC4417 and BV
DSS
of all the external
back-to-back P-channel MOSFETs.
In applications below 20V, transient voltage suppressors
may not be required if the voltage spikes are lower than the
BV
DSS
of the external P-channel MOSFETs and the LTC4417
Figure 9. Transient Voltage Suppression
FDD4685 FDD4685
M1 M2
24V WALL
ADAPTER
VS1 G1
V
OUT
LTC4417
INPUT
PARASITIC
INDUCTANCE
OUTPUT
PARASITIC
INDUCTANCE
C
V1
0.1µF
C
SN
R
SN
C
OUT
10µF
C
L
330µF
V
OUT
OR
4417 F09
D2
SMBJ26A
D1
SMBJ26CA
OR
+
SNUBBER