Datasheet

LTC2471/LTC2473
8
24713fb
For more information www.linear.com/LTC2471
applicaTions inForMaTion
After the completion of a conversion, the LTC2471/LTC2473
enters the SLEEP/NAP state and remains there until a valid
read/write is acknowledged. Following this condition, the
ADC transitions into the DATA INPUT/OUTPUT state.
While in the SLEEP/NAP state, the LTC2471/LTC2473’s
converters are powered down. This reduces the supply
current by approximately 70%. While in the NAP state
the reference remains powered up. The user can power
down both the reference and the converter by enabling
the sleep mode during the DATA INPUT/OUTPUT state.
Once the next conversion is complete with the sleep
mode enabled, the SLEEP state is entered and power is
reduced to 2μA (maximum). The reference is powered up
once a valid read/write is acknowledged. The reference
startup time is 12ms (if the reference and compensation
capacitor values are both 0.1μF). As the reference and
compensation capacitors are decreased, the startup time
is reduced (see Figure 3), but the transition noise increases
(see Figure 4).
Power-Up Sequence
When the power supply voltage (V
CC
) applied to the con-
verter is below approximately 2.1V, the ADC performs a
power-on reset. This feature guarantees the integrity of
the conversion result.
When V
CC
rises above this critical threshold, the converter
generates an internal power-on reset (POR) signal for ap
-
proximately 0.5ms. For proper operation V
DD
needs to be
restored to normal operating range (2.7V to 5.5V) before
the conclusion of the POR cycle. The POR signal clears all
internal registers. Following the POR signal, the LTC2471/
LTC2473 start a conversion cycle and follow the succes
-
sion of states shown in Figure 2. The reference startup
time following a POR is 12ms (C
COMP
= C
REFOUT
= 0.1μF).
The first conversion following power-up will be invalid
if the reference voltage has not completely settled (see
Figure 3). The first conversion following power up can be
discarded using the data abort command or simply read
and ignored. Depending on the value chosen for C
COMP
and C
REFOUT
, the reference startup can take more than
one conversion period, see Figure 3. If the startup time is
less than 1.2ms (833sps output rate) or 4.8ms (208sps
output rate) then conversions following the first period
are accurate to the device specifications. If the startup
time exceeds 1.2ms or 4.8ms then the user can wait the
appropriate time or use the fixed conversion period as
a startup timer by ignoring results within the unsettled
period. Once the reference has settled, all subsequent
conversion results are valid. If the user places the device
into the sleep mode (SLP = 1, reference powered down)
the reference will require a startup time proportional to
the value of C
COMP
and C
REFOUT
(see Figure 3).
Figure 4. Transition Noise RMS vs COMP and
Reference Capacitance
Figure 3. Reference Start-Up Time vs V
REF
and
Compensation Capacitance
CAPACITANCE (µF)
1
TIME (ms)
50
150
250
24713 F03
–50
0
100
200
0.1
0.01
0.001
V
CC
= 5.5V
V
CC
= 4.1V
V
CC
= 2.7V
0.001 0.01 0.10.0001
10
1
CAPACITANCE (µF)
TRANSITION NOISE (µV RMS)
24713 F04
0
5
10
15
20
25