Datasheet

LTC2471/LTC2473
10
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Figure 5. Definition of Timing for Fast/Standard Mode Devices on the I
2
C Bus
The LTC2471/LTC2473 can only be addressed as a slave.
It can only transmit the last conversion result. The serial
clock line, SCL, is always an input to the LTC2471/LTC2473
and the serial data line SDA is bidirectional. Figure 5 shows
the definition of the I
2
C timing.
The START and STOP Conditions
A START (S) condition is generated by transitioning SDA
from HIGH to LOW while SCL is HIGH. The bus is consid
-
ered to be busy after the START condition. When the data
transfer is finished, a STOP (P) condition is generated by
transitioning SDA from LOW to HIGH while SCL is HIGH.
The bus is free after a STOP is generated. START and STOP
conditions are always generated by the master.
When the bus is in use, it stays busy if a repeated START
(Sr) is generated instead of a STOP condition. The repeated
START timing is functionally identical to the START and
is used for reading from the device before the initiation
of a new conversion.
Data Transferring
After the START condition, the I
2
C bus is busy and data
transfer can begin between the master and the addressed
slave. Data is transferred over the bus in groups of nine
bits, one byte followed by one acknowledge (ACK) bit. The
master releases the SDA line during the ninth SCL clock
cycle. The slave device can issue an ACK by pulling SDA
LOW or issue a Not Acknowledge (NACK) by leaving the
SDA line HIGH impedance (the external pull-up resistor
will hold the line HIGH). Change of data only occurs while
the clock line (SCL) is LOW.
Output Data Format
After a START condition, the master sends a 7-bit address
followed by a read request (R) bit. The bit R is 1 for a
Read Request. If the 7-bit address matches the LTC2471/
LTC2473’s address (0010100 or 1010100, depending on
the state of the pin A0) the ADC is selected. When the
device is addressed during the conversion state, it does
SDA
SCL
S Sr P S
t
HD(STA)
t
HD(DAT)
t
SU(STA)
t
SU(STO)
t
SU(DAT)
t
LOW
t
HD(SDA)
t
SP
t
BUF
t
r
t
f
t
r
t
f
t
HIGH
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