Datasheet

LTC6946
20
6946fa
OPERATION
STAT Output
The STAT output pin is configured with the x[5:0] bits
of register h01. These bits are used to bit-wise mask, or
enable, the corresponding status flags of status register
h00, according to Equation 2. The result of this bit-wise
Boolean operation is then output on the STAT pin:
STAT = OR (Reg00[5:0] AND Reg01[5:0]) (2)
or expanded:
STAT = (UNLOCK AND x[5]) OR
(ALCHI AND x[4]) OR
(ALCLO AND x[3]) OR
(LOCK AND x[2]) OR
(THI AND x[1]) OR
(TLO AND x[0])
For example, if the application requires STAT to go high
whenever the ALCHI, ALCLO, or THI flags are set, then
x[4], x[3], and x[1] should be set to “1”, giving a register
value of h1A.
Block Power-Down Control
The LTC6946’s power-down control bits are located in
register h02, described in Table 11. Different portions of
the device may be powered down independently. Care must
be taken with the LSB of the register, the POR (power-on
reset) bit. When written to a “1”, this bit forces a full reset of
the part’s digital circuitry to its power-up default state.
Table 11. Serial Port Register Bit Field Summary
BITS DESCRIPTION DEFAULT
ALCCAL Auto Enable ALC During CAL Operation 1
ALCEN Always Enable ALC (Override) 1
ALCHI ALC Too Hi Flag
ALCLO ALC Too Low Flag
ALCMON Enable ALC Monitor for Status Flags Only 0
ALCULOK Enable ALC When PLL Unlocked 0
BD[3:0] Calibration B Divider Value h3
BST REF Buffer Boost Current 1
CAL Start VCO Calibration (auto clears) 0
CP[3:0] CP Output Current hB
CPCHI CP Enable Hi Voltage Output Clamp 1
CPCLO CP Enable Low Voltage Output Clamp 1
CPDN CP Pump Down Only 0
CPINV CP Invert Phase 0
CPMID CP Bias to Mid-Rail 1
CPRST CP Three-State 1
CPUP CP Pump Up Only 0
CPWIDE CP Extend Pulse Width 0
FILT[1:0] REF Input Buffer Filter h3
LKCT[1:0] PLL Lock Cycle Count h1
LKEN PLL Lock Indicator Enable 1
LKWIN[1:0] PLL Lock Indicator Window h2
LOCK PLL Lock Indicator Flag
MTCAL Mutes Output During Calibration 1
ND[15:0] N Divider Value (ND[15:0] > 31) h00FA
OD[2:0] Output Divider Value (0 < OD[2:0] < 7) h1
OMUTE Mutes RF Output 1
PART[4:0] Part code (h01 for LTC6946-1, h02 for
LTC6946-2, h03 for LTC6946-3 Version)
h01, h02, h03
PDALL Full Chip Power Down 0
PDOUT Powers Down O_DIV, RF Output Buffer 0
PDPLL Powers Down REF, REFO, R_DIV, PFD,
CPUMP, N_DIV
0
PDREFO Powers Down REFO 1
PDVCO Powers Down VCO, N_DIV 0
POR Force Power-On Reset 0
RD[9:0] R Divider Value (RD[9:0] > 0) h001
REV[2:0] Rev Code h2
RFO[1:0] RF Output Power h3
THI CP Clamp High Flag
TLO CP Clamp Low Flag
UNLOK PLL Unlock Flag
x[5:0] STAT Output OR Mask h04