Datasheet

LTC6946
16
6946fa
OPERATION
The VCO may be calibrated once the RD[9:0], ND[15:0],
and BD[3:0] bits are written. The reference frequency f
REF
must also be present and stable at the REF
±
inputs.
A calibration cycle is initiated each time the CAL bit is written
to “1” (the bit is self-clearing). The calibration cycle takes
between 12 and 14 cycles of the B divider output.
VCO Automatic Level Control (ALC)
The VCO uses an internal automatic level control (ALC)
algorithm to maintain an optimal amplitude on the VCO
resonator, and thus optimal phase noise performance. The
user has several ALC configuration and status reporting
options as seen in Table 8.
Table 8. ALC Bit Descriptions
BIT DESCRIPTION
ALCCAL Auto Enable ALC During CAL Operation
ALCEN Always Enable ALC (Overrides ALCCAL, ALCMON and
ALCULOK)
ALCHI ALC Too High Flag (Resonator Amplitude Too High)
ALCLO ALC Too Low Flag (Resonator Amplitude Too Low)
ALCMON Enable ALC Monitoring for Status Flags Only; Does NOT
Enable Amplitude Control
ALCULOK Auto Enable ALC when PLL Unlocked
Changes in the internal ALC output can cause extremely
small jumps in the VCO frequency. These jumps may be
acceptable in some applications but not in others. Use the
above table to choose when the ALC is active. The ALCHI
and ALCLO flags, valid only when the ALC is active or the
ALCMON bit is set, may be used to monitor the resonator
amplitude.
The ALC must be allowed to operate during or after a
calibration cycle. At least one of the ALCCAL, ALCEN or
ALCULOK bits must be set.
VCO (N) DIVIDER
The 16-bit N divider provides the feedback from the VCO
to the PFD. Its divide ratio N may be set to any integer
from 32 to 65535, inclusive. Use the ND[15:0] bits found
in registers h05 and h06 to directly program the N divide
ratio. See the Applications Information section for the
relationship between N and the f
REF
, f
PFD
, f
VCO
and f
RF
frequencies.
OUTPUT (O) DIVIDER
The 3-bit O divider can reduce the frequency from the VCO
to extend the output frequency range. Its divide ratio O
may be set to any integer from 1 to 6, inclusive, outputting
a 50% duty cycle even with odd divide values. Use the
OD[2:0] bits found in register h08 to directly program the
0 divide ratio. See the Applications Information section
for the relationship between O and the f
REF
, f
PFD
, f
VCO
and
f
RF
frequencies.
RF OUTPUT BUFFER
The low noise, differential output buffer produces a dif-
ferential output power of –6dBm to 3dBm, settable with
bits RFO[1:0] according to Table 9. The outputs may be
combined externally, or used individually. Terminate any
unused output with a 50Ω resistor to V
RF
+
.
Table 9. RFO[1:0] Programming
RFO[1:0} P
RF
(Differential) P
RF
(Single Ended)
0 –6dBm –9dBm
1 –3dBm –6dBm
2 0dBm –3dBm
3 3dBm 0dBm
Each output is open collector with 136Ω pull-up resistors
to V
RF
+
, easing impedance matching at high frequencies.
See Figure 6 for circuit details and the Applications Infor-
mation section for matching guidelines. The buffer may
be muted with either the OMUTE bit, found in register
h02, or by forcing the MUTE input low.
12
11
6946 F06
V
RF
+
V
RF
+
RF
+
136Ω136Ω
RF
–
MUTE
OMUTE
RFO[1:0]
9
MUTE
Figure 6. Simplified RF Interface Schematic