Datasheet

LTC2655
20
2655f
necessary if the bus capacitance is greater than 200pF.
The LTC2655 is a receive-only (slave) device. The master
can write to the LTC2655. The LTC2655 does not respond
to a read command from the master.
The START (S) and STOP (P) Conditions
When the bus is not in use, both SCL and SDA must be high.
A bus master signals the beginning of a communication
to a slave device by transmitting a START condition (see
Figure 1). A START condition is generated by transitioning
SDA from high to low while SCL is high. When the master
has fi nished communicating with the slave, it issues a STOP
condition. A STOP condition is generated by transitioning
SDA from low to high while SCL is high. The bus is then
free for communication with another I
2
C device.
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the lat-
est byte of information was received. The Acknowledge
related clock pulse is generated by the master. The master
releases the SDA line (HIGH) during the Acknowledge
clock pulse. The slave-receiver must pull down the SDA
bus line during the Acknowledge clock pulse so that it
remains a stable LOW during the HIGH period of this clock
pulse. The LTC2655 responds to a write by a master in
this manner. The LTC2655 does not acknowledge a read
(retains SDA HIGH during the period of the Acknowledge
clock pulse).
Chip Address
The state of CA0, CA1 and CA2 decides the slave address
of the part. The pins CA0, CA1 and CA2 can be each set
to any one of three states: V
CC
, GND or fl oat. This results
in 27 selectable addresses for the part. The slave address
assignments are shown in Table 2.
In addition to the address selected by the address pins,
the parts also respond to a global address. This address
allows a common write to all LTC2655 parts to be accom-
plished with one 3-byte write transaction on the I
2
C bus.
The global address is a 7-bit on-chip hardwired address
and is not selectable by CA0, CA1 and CA2. The addresses
corresponding to the states of CA0, CA1 and CA2 and
the global address are shown in Table 2. The maximum
capacitive load allowed on the address pins (CA0, CA1
and CA2) is 10pF, as these pins are driven during address
detection to determine if they are fl oating.
Table 2. Slave Address Map
CA2 CA1 CA0 A6 A5 A4 A3 A2 A1 A0
GND GND GND 0 0 1 0 0 0 0
GND GND FLOAT 0 0 1 0 0 0 1
GND GND V
CC
0010010
GND FLOAT GND 0 0 1 0 0 1 1
GND FLOAT FLOAT 0 1 0 0 0 0 0
GND FLOAT V
CC
0100001
GND V
CC
GND 0 1 0 0 0 1 0
GND V
CC
FLOAT 0 1 0 0 0 1 1
GND V
CC
V
CC
0110000
FLOAT GND GND 0 1 1 0 0 0 1
FLOAT GND FLOAT 0 1 1 0 0 1 0
FLOAT GND V
CC
0110011
FLOAT FLOAT GND 1 0 0 0 0 0 0
FLOAT FLOAT FLOAT 1 0 0 0 0 0 1
FLOAT FLOAT V
CC
1000010
FLOAT V
CC
GND 1 0 0 0 0 1 1
FLOAT V
CC
FLOAT 1 0 1 0 0 0 0
FLOAT V
CC
V
CC
1010001
V
CC
GND GND 1 0 1 0 0 1 0
V
CC
GND FLOAT 1 0 1 0 0 1 1
V
CC
GND V
CC
1100000
V
CC
FLOAT GND 1 1 0 0 0 0 1
V
CC
FLOAT FLOAT 1 1 0 0 0 1 0
V
CC
FLOAT V
CC
1100011
V
CC
V
CC
GND 1 1 1 0 0 0 0
V
CC
V
CC
FLOAT 1 1 1 0 0 0 1
V
CC
V
CC
V
CC
1110010
GLOBAL ADDRESS 1 1 1 0 0 1 1
OPERATION