Datasheet

LTC2655
18
2655f
TIMING DIAGRAM
Figure 1
V
IH(CA
n
)
/V
IL(CA
n
)
CAn
100
2655 TC01
GND
R
INH
/R
INL
/R
INF
V
DD
2655 TC02
Test Circuit 1
Test Circuit 2
TEST CIRCUITS
SDA
t
f
S
t
r
t
LOW
t
HD(STA)
ALL VOLTAGE LEVELS REFER TO V
IH(MIN)
AND V
IL(MAX)
LEVELS
t
HD(DAT)
t
SU(DAT)
t
SU(STA)
t
HD(STA)
t
SU(STO)
t
SP
t
BUF
t
r
t
f
t
HIGH
SCL
S P S
2655 F01
9TH CLOCK
OF 3RD
DATA BYTE
t
1
SCL
LDAC