Datasheet

LTC2945
5
2945fa
For more information www.linear.com/LTC2945
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive. All voltages are referenced to
ground, unless otherwise noted.
Note 3: An internal shunt regulator limits the INTV
CC
pin to a minimum of
5.9V. Driving this pin to voltages beyond 5.9V may damage the part. This
pin can be safely tied to higher voltages through a resistor that limits the
current below 35mA.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I
2
C INTERFACE TIMING
f
SCL(MAX)
Maximum SCL Clock Frequency 400 kHz
t
LOW
Minimum SCL Low Period 0.65 1.3 µs
t
HIGH
Minimum SCL High Period 50 600 ns
t
BUF(MIN)
Minimum Bus Free Time Between Stop/Start
Condition
0.12 1.3 µs
t
HD,STA(MIN)
Minimum Hold Time After (Repeated) Start
Condition
140 600 ns
t
SU,STA(MIN)
Minimum Repeated Start Condition Set-Up
Time
30 600 ns
t
SU,STO(MIN)
Minimum Stop Condition Set-Up Time 30 600 ns
t
HD,DATI(MIN)
Minimum Data Hold Time Input –100 0 ns
t
HD,DATO(MIN)
Minimum Data Hold Time Output 300 600 900 ns
t
SU,DAT(MIN)
Minimum Data Set-Up Time 30 100 ns
t
SP(MAX)
Maximum Suppressed Spike Pulse Width 50 110 250 ns
t
RST
Stuck Bus Reset Time SCL or SDAI Held Low 25 33 ms
C
X
SCL, SDAI Input Capacitance (Note 5) 5 10 pF
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
DD
is from 4V to 80V unless otherwise noted. (Note 2)
Note 4: Internal clamps limit the SCL and SDAI pins to a minimum of 5.9V.
Driving these pins to voltages beyond the clamp may damage the part. The
pins can be safely tied to higher voltages through resistors that limit the
current below 5mA.
Note 5: Guaranteed by design and not subject to test.
Note 6:
T
UE =
ACTUAL CODE
−
IDEAL CODE
( )
4096
× 100
%
where IDEAL CODE is derived from a straight line passing through Code 0
at 0V and Theoretical Code of 4096 at V
FS
.
Note 7: ΔSENSE is defined as V
SENSE
+ – V
SENSE
–