Datasheet

LTC2752
11
2752f
block DiagraM
16
3
CODE REGISTERS
SPAN REGISTERS
33
34
41
29
42
(37, 38) R
OFSB
(35, 36) REFB
(31, 32) R
INB
SROSCKSDIS2S1S0M-SPAN CS/LD LDACCLRRFLAG
GE
ADJB
R
COMB
I
OUT1B
I
OUT2BS
V
OSADJB
(39, 40) R
FBB
28
I
OUT2BF
9
I
OUT2AF
26131211192025242322
16
3
CODE REGISTERS
SPAN REGISTERS
DAC REG
DAC REG
4
3
44
8
43
R
OFSA
(47, 48)
REFA (1, 2)
R
INA
(5, 6)
GE
ADJA
R
COMA
I
OUT1A
I
OUT2AS
V
OSADJA
R
FBA
(45, 46)
DAC A
16-BIT WITH
SPAN SELECT
GND (7, 10, 15, 17, 18, 27, 30)
14
V
DD
16
INPUT REG
INPUT REG
INPUT REG
INPUT REG
DAC REG
DAC REG
DAC B
16-BIT WITH
SPAN SELECT
CONTROL AND READBACK LOGIC
POWER-ON
RESET
2752 BD
2.56M 2.56M
20k
20k
20k
20k