Datasheet

LTM4628
15
4628fe
For more information www.linear.com/LTM4628
APPLICATIONS INFORMATION
Figure 5. Operating Frequency vs f
SET
Pin Voltage
Frequency Selection and Phase-Locked Loop
(MODE_PLLIN and f
SET
Pins)
The LTM4628 device is operated over a range of frequencies
to improve power conversion efficiency. It is recommended
to operate the lower output voltages or lower duty cycle
conversions at lower frequencies to improve efficiency by
lowering power MOSFET switching losses. Higher output
voltages or higher duty cycle conversions can be operated
at higher frequencies to limit inductor ripple current. The
efficiency graphs will show an operating frequency chosen
for that condition.
The LTM4628 switching frequency can be set with an
external resistor from the f
SET
pin to SGND. An accurate
10µA current source into the resistor will set a voltage
that programs the frequency or a DC voltage can be
applied. Figure 5 shows a graph of frequency setting
verses programming voltage. An external clock can be
applied to the MODE_PLLIN pin from 0V to INTV
CC
over
a frequency range of 400kHz to 780kHz. The clock input
high threshold is 1.6V and the clock input low threshold
is 0.5V. The LTM4628 has the PLL loop filter components
on board. The frequency setting resistor should always
be
present to set the initial switching frequency before
locking to an external clock. Both regulators will operate
in continuous mode while being externally clocked.
The output of the PLL phase detector has a pair of comple
-
mentary current
sources that charge and discharge the
internal filter network. When the external clock is applied
the f
SET
frequency resistor is disconnected with an internal
switch, and the current sources control the frequency
adjustment to lock to the incoming external clock. When
no external clock is applied, then the internal switch is on,
thus connecting the external f
SET
frequency set resistor
for free run operation.
Minimum On-Time
Minimum on-time t
ON
is the smallest time duration that
the LTM4628 is capable of turning on the top MOSFET on
either channel. It is determined by internal timing delays,
and the gate charge required to turn on the top MOSFET.
Low duty cycle applications may approach this minimum
on-time limit and care should be taken to ensure that:
V
OUT
V
IN
• FREQ
> t
ON(MIN)
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated, but
the output ripple and current will increase. The minimum
on-time can be increased by lowering the switching fre
-
quency. A good
rule
of thumb is to use an 110ns on-time.
f
SET
PIN VOLTAGE (V)
0
FREQUENCY (kHz)
900
800
600
400
100
200
700
500
300
0
2
4628 F05
2.51 1.50.5