Datasheet
LTC2470/LTC2472
8
24702fb
For more information www.linear.com/LTC2470
applicaTions inForMaTion
complete, the SLEEP state is entered and power is reduced
to 2μA (maximum). The reference is powered up once CS
is brought low. The reference startup time is 12ms (if the
reference and compensation capacitor values are both
0.1μF). As the reference and compensation capacitors are
decreased, the startup time is reduced (see Figure 3), but
the transition noise increases (see Figure 4).
Upon entering the DATA INPUT/OUTPUT state, SDO
outputs the sign (D15) of the conversion result. During
this state, the ADC shifts the conversion result serially
through the SDO output pin under the control of the SCK
input pin. There is no latency in generating this data and
the result corresponds to the last completed conversion.
A new bit of data appears at the SDO pin following each
falling edge detected at the SCK input pin and appears
from MSB to LSB. The user can reliably latch this data
on every rising edge of the external serial clock signal
driving the SCK pin.
During the DATA INPUT/OUTPUT state, the LTC2470/
LTC2472 can be programmed to SLEEP or NAP (default)
and the output rate can be updated. Data is shifted into
the device through the SDI pin on the rising edge of SCK.
The input word is 4 bits. If the first bit EN1 = 1 and the
second bit EN2 = 0 the device is enabled for programming.
The following two bits (SPD and SLP) will be written into
the device. SPD is used to select the output rate. If SPD =
0 (Default) the output rate is 208sps and SPD = 1 sets a
833sps output rate. The next bit (SLP) enables the sleep
or nap mode. If SLP = 0 (default) the reference remains
powered up at the end of each conversion cycle. If SLP =
1, the reference powers down following the next conver
-
sion cycle. The remaining 12
SDI
input bits are ignored
(don’t care).
SDI may also be tied directly to GND or V
DD
in order to
simplify the user interface. If SDI is tied LOW the output
rate is 208sps and if SDI is tied HIGH the output rate is
833sps. The reference sleep mode is disabled if SDI is
tied to GND or V
DD
.
The DATA INPUT/OUTPUT state concludes in one of two
different ways. First, the DATA INPUT/OUTPUT state opera
-
tion is completed once all 16 data bits have been shifted
out and the clock then goes low. This corresponds to the
16
th
falling edge of SCK. Second, the DATA INPUT/OUT-
PUT state can be aborted at any time by a LOW-to-HIGH
transition on the CS input.
Following either one of these
two actions, the LTC2470/LTC2472 will enter the CONVERT
state and initiate a new conversion cycle.
Power-Up Sequence
When the power supply voltage (V
CC
) applied to the con-
verter is below approximately 2.1V, the ADC performs a
power-on reset. This feature guarantees the integrity of
the conversion result.
When V
CC
rises above this critical threshold, the converter
generates an internal power-on reset (POR) signal for
approximately 0.5ms. For proper operation V
DD
needs
to be restored to normal operating range (2.7V to 5.5V)
Figure 4. Transition Noise RMS vs COMP and
Reference Capacitance
Figure 3. Reference Start-Up Time vs V
REF
and
Compensation Capacitance
CAPACITANCE (µF)
1
TIME (ms)
50
150
250
24702 F03
–50
0
100
200
0.1
0.01
0.001
V
CC
= 5.5V
V
CC
= 4.1V
V
CC
= 2.7V
0.001 0.01 0.10.0001
10
1
CAPACITANCE (µF)
TRANSITION NOISE (µV RMS)
24702 F04
0
5
10
15
20
25