Datasheet

LTC2470/LTC2472
7
24702fb
For more information www.linear.com/LTC2470
applicaTions inForMaTion
CONVERTER OPERATION
Converter Operation Cycle
The LTC2470/LTC2472 are low power, delta sigma, analog
to digital converters with a simple SPI interface and a user
selected 208sps/833sps output rate (see Figure 1). The
LTC2472 has a fully differential input while the LTC2470 is
single-ended. Both are pin and software compatible. Their
operation is composed of three distinct states: CONVERT,
SLEEP/NAP, and DATA INPUT/OUTPUT. The operation
begins with the CONVERT state (see Figure 2). Once the
conversion is finished, the converter automatically pow
-
ers down (NAP) or under user control, both the converter
and reference are powered down (SLEEP). The conversion
result is held in a static register while the device is in this
state. The cycle concludes with the DA
TA INPUT/OUTPUT
state. Once all 16-bits are read or an abort is initiated the
device begins a new conversion.
The CONVER
T state duration is determined by the
LTC2470/LTC2472 conversion time (nominally 4ms or
1ms depending on the selected output rate). Once started,
this operation can not be aborted except by a low power
supply condition (V
CC
< 2.1V) which generates an internal
power-on reset signal.
After the completion of a conversion, the LTC2470/LTC2472
enters the SLEEP/NAP state and remains there until the
chip select is LOW (CS = LOW). Following this condition,
the ADC transitions into the DATA INPUT/OUTPUT state.
Figure 2. LTC2470/LTC2472 State Transition Diagram
While in the SLEEP/NAP state, when chip select input is
HIGH (CS = HIGH), the LTC2470/LTC2472’s converters are
powered down. This reduces the supply current by approxi
-
mately 70%. While in the NAP state the reference remains
powered up. The user can power down both the reference
and the converter by enabling the sleep mode during the
DATA INPUT/OUTPUT state. Once the next conversion is
DATA INPUT/OUTPUT
SLEEP/NAP
CONVERT
POWER-ON RESET
YES
24602
F02
16TH FALLING
EDGE OF SCK
OR
CS = HIGH?
CS = LOW?
NO YES
NO
block DiagraM
Figure 1. Functional Block Diagram
ΔΣ A/D
CONVERTER
DECIMATING
SINC FILTER
SDO
REFOUT COMP
REF
–
IN
+
(IN)
IN
–
(GND)
SCK
CS
24702 BD
–
ΔΣ A/D
CONVERTER
INTERNAL
REFERENCE
( ) PARENTHESIS INDICATE LTC2470
SPI
INTERFACE
INTERNAL
OSCILLATOR
1
V
CC
122
3
5
6
SDI
4
8
GND7, 11, 13 DD PACKAGE
7, 11 MS PACKAGE
9
10