Datasheet

LTC2470/LTC2472
16
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For more information www.linear.com/LTC2470
applicaTions inForMaTion
In order for the reference to remain stable, the capacitor
placed on the COMP pin must be greater than or equal
to the capacitor tied to the REFOUT pin. The REFOUT pin
cannot be overridden by an external voltage.
Depending on the size of the capacitors tied to the REFOUT
and COMP pins, the internal reference has a corresponding
start up time. This start up time is typically 12ms when
0.1μF capacitors are used. The first conversion following
power up can be discarded using the data abort com
-
mand or simply read and ignored. Depending on the value
chosen for C
COMP
and C
REFOUT
, the reference startup can
take more than one conversion period, see Figure 3. If the
startup time is less than 1.2ms (833sps output rate) or
4.8ms (208sps output rate) then conversions following
the first period are accurate to the device specifications.
If the startup time exceeds 1.2ms or 4.8ms then the user
can wait the appropriate time or use the fixed conversion
period as a startup timer by ignoring results within the
unsettled period. Once the reference has settled all sub
-
sequent conversion results are valid. If the user places the
device into the sleep mode (SLP = 1, reference powered
down) the reference will require a startup time proportional
to the value of C
COMP
and C
REFOUT
, see Figure 3.
If the reference is put to sleep (program SLP = 1 and CS =
1) the reference is powered down after the next conversion.
This last conversion result is valid. On CS falling edge,
the reference is powered back up. In order to ensure the
reference output has settled before the next conversion,
the power up time can be extended by delaying the data
read after the falling edge of CS. Once all 16 bits are read
from the device or CS is brought HIGH, the next conver
-
sion automatically begins. In the default operation, the
reference remains powered up at the conclusion of the
conversion cycle.
Driving V
IN
+
and V
IN
–
The input drive requirements can best be analyzed using
the equivalent circuit of Figure 16. The input signal V
SIG
is
connected to the ADC input pins (IN
+
and IN
–
) through an
equivalent source resistance R
S
. This resistor includes both
the actual generator source resistance and any additional
optional resistors connected to the input pins. Optional
input capacitors C
IN
are also connected to the ADC input
pins. This capacitor is placed in parallel with the input
parasitic capacitance C
PAR
. This parasitic capacitance
includes elements from the printed circuit board (PCB)
Figure 16. LTC2470/LTC2472 Input Drive Equivalent Circuit
I
LEAK
I
LEAK
R
SW
15k
(TYP)
I
CONV
C
IN
IN
+
(LTC2472)
IN
(LTC2470)
V
CC
SIG
+
SIG
–
R
S
C
EQ
0.35pF
(TYP)
C
PAR
+
–
24702 F16
I
LEAK
I
LEAK
R
SW
15k
(TYP)
I
CONV
C
IN
IN
–
(LTC2472)
V
CC
R
S
C
EQ
0.35pF
(TYP)
C
PAR
+
–
and the associated input pin of the ADC. Depending on the
PCB layout, C
PAR
has typical values between 2pF and 15pF.
In addition, the equivalent circuit of Figure 16 includes the
converter equivalent internal resistor R
SW
and sampling
capacitor C
EQ
.
There are some immediate trade-offs in R
S
and C
IN
without
needing a full circuit analysis. Increasing R
S
and C
IN
can
give the following benefits:
1) Due to the LTC2470/LTC2472’s input sampling algo
-
rithm, the input current drawn by either IN
+
or IN
–
over
a conversion cycle is typically 50nA. A high R
S
• C
IN
attenuates the high frequency components of the input
current, and R
S
values up to 1k result in <1LSB error.
2) The bandwidth from V
SIG
is reduced at the input pins
(IN
+
, IN
–
or IN). This bandwidth reduction isolates the
ADC from high frequency signals, and as such provides
simple anti-aliasing and input noise reduction.
3) Switching transients generated by the ADC are attenu
-
ated before they go back to the signal source.