Datasheet
LTC2470/LTC2472
14
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For more information www.linear.com/LTC2470
applicaTions inForMaTion
2-Wire Operation
The 2-wire operation modes, while reducing the number
of required control signals, should be used only if the
LTC2470/LTC2472 low power sleep capability is not re
-
quired. In addition the option to abort serial data transfers
is no longer available. Hardwire CS to GND for 2-wire
operation. T
ie SDI LOW for 208sps output rate and SDI
HIGH for 833sps output rate.
Figure 13 shows a 2-wire operation sequence which uses
an idle-high (CPOL = 1) serial clock signal. Following a
conversion cycle, the ADC enters the data output state
and the SDO output transitions from HIGH to LOW. Sub
-
sequently 16 clock pulses are applied to the SCK input in
order
to serially
shift the 16 bit result. Finally, the 17th
clock pulse is applied to the SCK input in order to trigger
a new conversion cycle.
Figure 14 shows a 2-wire operation sequence which uses
an idle-low (CPOL = 0) serial clock signal. Following a
conversion cycle, the LTC2470/LTC2472 enters the DATA
OUTPUT state. At this moment the SDO pin outputs the
sign (D15) of the conversion result. The user must use
external timing in order to determine the end of conversion
and result availability. Subsequently 16 clock pulses are
applied to SCK in order to serially shift the 16-bit result.
The 16th clock falling edge triggers a new conversion
cycle. Tie SDI LOW for 208sps output rate and SDI HIGH
for 833sps output rate.
PRESERVING THE CONVERTER ACCURACY
The LTC2470/LTC2472 are designed to minimize the
conversion result’s sensitivity to device decoupling, PCB
layout, anti-aliasing circuits, line and frequency pertur
-
bations. Nevertheless, in order to preserve the high ac-
curacy capability of this part, some simple precautions
are desirable.
Digital Signal Levels
Due to the nature of CMOS logic, it is advisable to keep input
digital signals near GND or V
CC
. Voltages in the range of
0.5V to V
CC
– 0.5V may result in additional current leakage
Figure 13. 2-Wire, Idle-High (CPOL = 1) Serial Clock, Operation Example
Figure 14. 2-Wire, Idle-Low (CPOL = 0) Serial Clock Operation Example
D
15
D
14
D
13
D
12
D
2
D
1
D
0
SD0
clk
1
clk
2
clk
3
clk
4
clk
15
clk
16
clk
17
SCK
CONVERT
SDI = 0 OR 1
CONVERTDATA OUTPUT
CS = LOW
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D
15
D
14
D
13
D
12
D
2
D
1
D
0
SD0
CS = LOW
clk
1
clk
2
clk
3
clk
14
clk
4
clk
15
clk
16
SCK
CONVERT CONVERTDATA OUTPUT
SDI = 0 OR 1
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