Datasheet

LTC2470/LTC2472
12
24702fb
For more information www.linear.com/LTC2470
Serial Clock Idle-Low (CPOL = 0) Examples
In Figure 8, following a conversion cycle the LTC2470/
LTC2472 automatically enters the NAP state. The device
reference will power down if the SLP bit was set high
prior to the just completed conversion and CS is HIGH.
Once CS goes low, the reference powers up. The user
determines data availability (and the end of conversion)
based upon external timing. The user then pulls CS low
(CS = ↓) and uses 16 clock cycles to transfer the result.
Following the 16th rising edge of the clock, CS is pulled high
(CS = ↑), which triggers a new conversion.
The timing diagram in Figure 9 is identical to that of Figure 8,
except in this case a new conversion is triggered by SCK.
The 16th SCK falling edge triggers a new conversion cycle
and the CS signal is subsequently pulled high.
Examples of Aborting Cycle using CS
For some applications, the user may wish to abort the I/O
cycle and begin a new conversion. If the LTC2470/LTC2472
are in the data input/output state, a CS rising edge clears
the remaining data bits from the output register, aborts
the output cycle and triggers a new conversion. Figure
10 shows an example of aborting an I/O with idle-high
(CPOL = 1) and Figure 11 shows an example of aborting
an I/O with idle-low (CPOL = 0).
A new conversion cycle can be triggered using the CS
signal without having to generate any serial clock pulses
as shown in Figure 12. If SCK is held at a low logic level,
after the end of a conversion cycle, a new conversion op-
eration can be triggered by pulling CS low and then high.
When CS is pulled low (CS = LOW), SDO will output the
sign (D15) of the result of the just completed conversion.
While a low logic level is maintained at SCK pin and
CS
is subsequently pulled high (CS = HIGH) the remaining
15 bits of the result (D14:D0) are discarded and a new
conversion cycle starts.
Following the aborted I/O, additional clock pulses in the
CONVERT state are acceptable, but excessive signal tran-
sitions on SCK can potentially create noise on the ADC
during the conversion, and thus may negatively influence
the conversion accuracy.
applicaTions inForMaTion
Figure 8. Idle-Low (CPOL = 0) Clock. CS Triggers a New Conversion
D
15
D
14
D
13
D
12
D
2
D
1
D
0
clk
1
clk
2
clk
3
clk
4
clk
14
clk
15
clk
16
SCK
SD0
CONVERT CONVERTNAP DATA OUTPUT
24702 F08
CS
SDI
EN2 SPD SLP
EN1
Figure 7. Idle-High (CPOL = 1) Clock Operation Example.
A 17th Clock Pulse is Used to Trigger a New Conversion Cycle
D
15
D
14
D
13
D
12
D
2
D
1
D
0
SD0
clk
1
clk
2
clk
3
clk
4
clk
15
clk
16
clk
17
SCK
CONVERT CONVERTNAP DATA OUTPUT
24702 F07
CS
SDI
EN2 SPD SLP
EN1