Datasheet

LTC4226
14
4226f
applicaTions inForMaTion
pin is pulled below V
FTMR(L)
. The GATE to OUT voltage
can ramp up for Auto-Retry mode if the ON pin is high
and V
CC
is not in UVLO.
When the MOSFET current exceeds the circuit breaker
threshold but remains below the current limit the fault
time is given by:
t
CB
= C
T
•
1.23V
I
FTMR(CB)
2
( )
When the current limit is active the fault time is given by:
t
LIMIT
= C
T
•
1.23V
I
FTMR(CL)
(3)
During active current limiting, a large MOSFET drain to
source voltage can appear, and t
LIMIT
should be selected
appropriately based on the worst MOSFET safe-operating-
area with the OUT pin shorted to ground.
A I
FTMR(RST)
pull-down source is active when resetting
the fault status. The current sources at the FTMR pin can
be overdriven externally. The FTMR pin can be pulled high
externally above V
FTMR(H)
to force a fault status or the FTMR
pin can be pulled low externally towards ground to force
a reset status. Both the FAULT and GATE pins behave the
same way for externally driven FTMR as described above
for internal mode. A prolonged external pull-down is not
recommended as it may mask normal FTMR operation.
Selecting Current Limit to Circuit Breaker Ratio
The ratio of the current limit voltage V
LIMIT
and circuit
breaker voltage V
CB
can be configured to allow low duty
cycle, high crest factor load events like hard drive spin
up to operate above the maximum average load current
without invoking current limit. Avoiding current limit events
is a good practice as the load voltage is not glitched un-
necessarily by the current
limit amplifier
and the MOSFET
power dissipation is kept low. The unlatched CLS pin has
three input states (low, open and high). This pin config-
ures both Hot Swap channels simultaneously the preset
current limit voltage V
LIMIT
to approximately 1.5×, 2× or
3× of 1.15 • V
CB
. However, higher current limit settings
will result in higher MOSFET power dissipation in the
event of a load short. Proper choice of the MOSFET must
accommodate high MOSFET power dissipation under the
worst case short-circuit. There are three I
FTMR(CL)
, each
corresponds with a V
LIMIT
selected by the CLS input. The
typical MOSFET SOA (safe operating area) has a constant
P
2
t characteristic for single narrow (<10ms) pulse dissipa-
tion. An increase in current (V
LIMIT
) for constant MOSFET
drain/source voltage results in square reduction in allowed
stress duration t
LIMIT
(or square increase in I
FTMR(CL)
).
The CLS pin is internally pulled to 1.23V. If it is driven
by a three-state output, the maximum allowable open-
circuit leakage is ±2µA. The driving output must source
or sink more than 10µA in the high or low state. If the
CLS trace crosses noisy digital signal lines, an RC filter
close to
the CLS pin will filter noise pickup (as shown in
Figure 1: R5/C3).
Auto-Retry vs Latchoff
The LTC4226-2 (automatic retry) version resets the FTMR
pin after a 0.5 second delay following a FTMR(H) com-
parator timeout if the V
CC
voltage remains above the 4V
undervoltage lockout threshold V
CC(UVL)
and the ON pin
remains above its 1.23V V
ON
threshold. This retry delay
can be terminated to force a 50ms delay restart by cycling
V
CC
below the V
CC(UVL)
undervoltage threshold or a 10ms
delay restart by cycling the ON pin below the V
ON
threshold.
The latchoff option (LTC4226-1) does not reset FTMR(L)
comparator automatically. It requires voltage cycling at
either the ON pin or the V
CC
pin to reset FTMR pin.
Resetting Faults
The circuit breaker fault can be reset by cycling the ON pin
below and then above the ON comparator threshold. There
is a turn on delay of 10ms after the ON pin transitions high.
Alternatively, the V
CC
pin can be cycled below and then
above the undervoltage lockout threshold to reset faults.
There is a turn on delay of 50ms after the V
CC
pin exits
the undervoltage lockout.
The
FTMR pin reset begins with the FTMR pin pulled down
with 100µA to ground. This is followed by a start-up with
a 10µA FAULT pin pull-up and a 9µA GATE pin pull-up.