Datasheet

LTC4227
17
422712fa
For more information www.linear.com/LTC4227
applicaTions inForMaTion
the INTV
CC
pin, as close as possible between INTV
CC
and
GND. Also place C
CP1
near the CPO1 and IN1 pins, and
C
CP2
near the CPO2 and IN2 pins. The transient voltage
suppressors, Z1 and Z2, when used, should be mounted
close to the LTC4227 using short lead lengths.
Prioritizing Supplies with D2ON
Figure 8 shows a diode-OR application where a resistive
divider connected from IN1 at the D2ON pin can suppress
the turn-on of the ideal diode MOSFET, M
D2
, in the IN2
supply path. When the IN1 supply voltage falls below 2.8V,
it allows the ideal diode MOSFET, M
D2
, to turn on, causing
the diode-OR output to be switched from the main 3.3V
supply at IN1 to the auxiliary 3.3V supply at IN2. This
configuration permits the load to be supplied from a lower
IN1 supply as compared to IN2 until IN1 falls below the
M
D2
turn-on threshold. The threshold value used should
not allow the IN1 supply to be operated at more than one
diode voltage below IN2. Otherwise, M
D2
conducts through
the MOSFET ’s body diode. The resistive divider connected
from SENSE
+
at the ON pin provides the undervoltage
threshold of 2.6V for the diode-OR output supply.
D G
D S
D S
D S
S D
S D
S D
G D
S D
S D
S D
G D
•••
•
•
•
•
•
•
• •
•
•••
Z2
Z1
R
S
M
H
PowerPAK SO-8
M
D1
PowerPAK SO-8
M
D2
PowerPAK SO-8
WIN1
VIA TO IN1
CURRENT FLOW
TO LOAD
C
CP2
4227 F07
20 19 18 17
7
1
2
3
4
5
6
16
15
14
13
12
11
8 9 10
LTC4227UFD
C
CP1
R
H
C1
OUT
W
WIN2
CURRENT FLOW
TO LOAD
TRACK WIDTH W:
0.03" PER AMPERE
ON 1oz Cu FOIL
VIA TO CPO1
VIA TO DGATE2
VIA TO GND PLANE
VIA TO GND PLANE
VIA TO GND PLANE
VIA TO DGATE1
Figure 7. Recommended PCB Layout for Power MOSFETs and Sense Resistor