Datasheet

LTC4227
8
422712fa
For more information www.linear.com/LTC4227
block DiagraM
+
–
+
–
A1
+
–
GA1
12V 12V
HGATE
OUT
CPO1
DGATE1
ON
CPO2
DGATE2
65mV
IN1
SENSE
+
SENSE
–
IN2
10µA
+
–
50mV
ECB
+
–
25mV
HGATE ON
1.235V
0.6V
2.2V
10µA
INTV
CC
CP1
25mV
+
–
100µA
INTV
CC
INTV
CC
100µA
+
–
INTV
CC
+
–
CHARGE
PUMP 1
f = 2MHz
GATE
DRIVER
CHARGE
PUMP 2
f = 2MHz
GA2
100µA
INTV
CC
2µA
INTV
CC
INTV
CC
+
–
FAULT RESET
CP2
CP3
+
–
1.235V
DGATE2 OFF
CP4
+
–
1.235V
0.2V
CP5
+
–
CP6
+
–
1.235V
CARD PRESENCE DETECT
LOGIC
+
–
D2ON
TMR
*UFD PACKAGE ONLY
EN*
10µA
10µA
UV1
GND
422712 BD
FAULT*
PWRGD
+
–
NC*
EXPOSED PAD*
1.9V
SENSE
+
UV2
+
–
5V LDO
12V
limit circuit controls HGATE to limit the voltage between
SENSE
+
and SENSE
–
to 65mV. A circuit breaker trips when
the sense voltage exceeds 50mV for more than a fault filter
delay configured at the TMR pin.
TMR: Timer Capacitor Terminal. Connect a capacitor
between this pin and ground to set a 12ms/µF duration
for current limit before the external Hot Swap MOSFET
is turned off. The duration of the off-time is 617ms/µF,
resulting in a 2% duty cycle.
pin FuncTions