Datasheet

LTC4227
14
422712fa
For more information www.linear.com/LTC4227
applicaTions inForMaTion
There is a 10µs glitch filter on the ON pin to reject supply
glitches. By placing a filter capacitor, C
F
, with the resis-
tive divider at the ON pin, the glitch filter delay is further
extended by the RC time constant to prevent any false fault.
Power Good Monitor
Internal circuitry monitors the MOSFET gate overdrive
between the HGATE and OUT pins. The power good sta
-
tus for the supply is reported via the open-drain output,
PWRGD. It is normally pulled high by an external pull-up
resistor or the internal 10µA pull-up. The power good
output asserts low when the gate overdrive exceeds 4.2V
during the HGATE start-up. Once asserted low, the power
good status is latched and can only be cleared by pulling
the ON pin low, toggling the EN pin from low to high, or
INTV
CC
entering undervoltage lockout. The power good
output continues to pull low while HGATE is regulating in
active current limit, but pulls high when the circuit breaker
times out and pulls the HGATE pin low.
CPO and DGATE Start-Up
The CPO and DGATE pin voltages are initially pulled up
to a diode below the IN
pin when first powered up. CPO
starts ramping up 7µs after INTV
CC
clears its undervolt-
age lockout level. Another 40µs later, DGATE also starts
ramping up with CPO. The CPO ramp rate is determined
by the CPO pull-up current into the combined CPO and
DGATE pin capacitances. An internal clamp limits the CPO
pin voltage to 12V above the IN pin, while the final DGATE
pin voltage is determined by the gate drive amplifier. An
internal 12V clamp limits the DGATE pin voltage above IN.
MOSFET Selection
The LTC4227 drives N-channel MOSFETs to conduct the
load current. The important features of the MOSFETs are
on-resistance, R
DS(ON)
, the maximum drain-source volt-
age, BV
DSS
, and the threshold voltage.
The gate drive for the ideal diode MOSFET and Hot Swap
MOSFET is guaranteed to be greater than 5V and 4.8V
respectively when the supply voltages at IN1 and IN2 are
between 2.9V and 7V. When the supply voltages at IN1
and IN2 are greater than 7V, the gate drive is guaranteed
Figure 6. Auto-Retry Sequence After a Fault
Supply Undervoltage Monitor
The ON pin functions as a turn-on control and an input
supply monitor. A resistive
divider connected between
the supply diode-OR output (SENSE
+
) and GND at the
ON pin monitors the supply undervoltage condition. The
undervoltage threshold is set by proper selection of the
resistors, and is given by:
V
IN(UVTH)
= 1+
R2
R1






• V
ON(TH)
where V
ON(TH)
is the ON rising threshold (1.235V).
An undervoltage fault occurs if the diode-OR output supply
falls below its undervoltage threshold for longer than 20µs.
The FAULT pin will not be pulled low. If the ON pin voltage
falls below 1.155V but remains above 0.6V, the Hot Swap
MOSFET is turned off by a 300µA pull-down from HGATE
to ground. The Hot Swap MOSFET turns back on instantly
without the debounce timing cycle when the diode-OR
output supply rises above its undervoltage threshold.
However, if the ON pin voltage drops below 0.6V, it turns
off the Hot Swap MOSFET and clears the fault latches. The
Hot Swap MOSFET turns back on only after a debounce
timing cycle when the diode-OR output supply is restored
above its undervoltage threshold. The ideal diode MOSFETs
are not affected by the undervoltage fault conditions.
If both IN supplies fall until the internally generated sup
-
ply, INTV
CC
, drops below its 2.2V UVLO threshold, all the
MOSFETs are turned off and the fault latches are cleared.
Operation resumes from a fresh start-up cycle when the
input supplies are restored and INTV
CC
exceeds its UVLO
threshold.
TMR
1V/DIV
HGATE
5V/DIV
FAULT
10V/DIV
I
LOAD
10A/DIV
100ms/DIV
4227 F06