Datasheet

19
21421012fa
LTC2142-12/
LTC2141-12/LTC2140-12
TIMING DIAGRAMS
Double Data Rate LVDS Output Mode Timing
All Outputs Are Differential and Have LVDS Levels
t
D
•
•
•
t
D
t
C
t
C
t
L
BIT 0
A-6
BIT 1
A-6
BIT 0
A-5
BIT 1
A-5
BIT 0
A-4
BIT 1
A-4
BIT 0
A-3
BIT 1
A-3
BIT 0
A-2
BIT 10
A-6
BIT 11
A-6
BIT 10
A-5
BIT 11
A-5
BIT 10
A-4
BIT 11
A-4
BIT 10
A-3
BIT 11
A-3
BIT 10
A-2
ENC
–
ENC
+
D1_0_1
+
D1_10_11
+
•
•
•
BIT 0
B-6
BIT 1
B-6
BIT 0
B-5
BIT 1
B-5
BIT 0
B-4
BIT 1
B-4
BIT 0
B-3
BIT 1
B-3
BIT 0
B-2
BIT 10
B-6
BIT 11
B-6
BIT 10
B-5
BIT 11
B-5
BIT 10
B-4
BIT 11
B-4
BIT 10
B-3
BIT 11
B-3
BIT 10
B-2
OF
B-6
OF
A-6
OF
B-5
OF
A-5
OF
B-4
OF
A-4
OF
B-3
OF
A-3
OF
B-2
D2_0_1
+
D2_10_11
+
CLKOUT
+
CLKOUT
–
OF2_1
+
D1_0_1
–
D1_10_11
–
D2_0_1
–
D2_10_11
–
OF2_1
–
21421012 TD03
t
H
t
AP
A + 1
A + 2
A + 4
A + 3
A
CH 1
ANALOG
INPUT
t
AP
B + 1
B + 2
B + 4
B + 3
B
CH 2
ANALOG
INPUT
A6
t
S
t
DS
A5 A4 A3 A2 A1 A0 XX
D7 D6 D5 D4 D3 D2 D1 D0
XX XX XX XX XX XX XX
CS
SCK
SDI
R/W
SDO
HIGH IMPEDANCE
SPI Port Timing (Readback Mode)
SPI Port Timing (Write Mode)
t
DH
t
DO
t
SCK
t
H
A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
21421012 TD04
CS
SCK
SDI
R/W
SDO
HIGH IMPEDANCE