Datasheet
7
21421012fa
LTC2142-12/
LTC2141-12/LTC2140-12
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 9)
SYMBOL PARAMETER CONDITIONS
LTC2142-12 LTC2141-12 LTC2140-12
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
CMOS Output Modes: Full Data Rate and Double Data Rate
V
DD
Analog Supply Voltage (Note 10)
l
1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
OV
DD
Output Supply Voltage (Note 10)
l
1.1 1.8 1.9 1.1 1.8 1.9 1.1 1.8 1.9 V
I
VDD
Analog Supply Current DC Input
Sine Wave Input
l
50.9
51.3
57 35.9
36.2
41 26.9
27
32 mA
mA
I
OVDD
Digital Supply Current Sine Wave Input, OV
DD
= 1.2V 3.8 2.4 1.5 mA
P
DISS
Power Dissipation DC Input
Sine Wave Input, OV
DD
= 1.2V
l
91.6
96.9
103 64.6
68
74 48.4
50.4
57.6 mW
mW
LVDS Output Mode
V
DD
Analog Supply Voltage (Note 10)
l
1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
OV
DD
Output Supply Voltage (Note 10)
l
1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
I
VDD
Analog Supply Current Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
52.6
53.8 61
37.4
38.7 45
28.3
29.5 35.5
mA
mA
I
OVDD
Digital Supply Current
(0V
DD
= 1.8V)
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
30
57.4 67
29.6
57.1 67
29.3
56.8 67
mA
mA
P
DISS
Power Dissipation Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
149
200 231
121
172 202
104
155 185
mW
mW
All Output Modes
P
SLEEP
Sleep Mode Power 1 1 1 mW
P
NAP
Nap Mode Power 10 10 10 mW
P
DIFFCLK
Power Increase with Differential Encode Mode Enabled
(No Increase for Nap or Sleep Modes)
20 20 20 mW
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS
LTC2142-12 LTC2141-12 LTC2140-12
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
f
S
Sampling Frequency (Note 10)
l
1 65 1 40 1 25 MHz
t
L
ENC Low Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
7.3
2
7.69
7.69
500
500
11.88
2
12.5
12.5
500
500
19
2
20
20
500
500
ns
ns
t
H
ENC High Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
7.3
2
7.69
7.69
500
500
11.88
2
12.5
12.5
500
500
19
2
20
20
500
500
ns
ns
t
AP
Sample-and-Hold
Acquisition Delay Time
000ns
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)
t
D
ENC to Data Delay C
L
= 5pF (Note 8)
l
1.1 1.7 3.1 ns
t
C
ENC to CLKOUT Delay C
L
= 5pF (Note 8)
l
1 1.4 2.6 ns
t
SKEW
DATA to CLKOUT Skew t
D
– t
C
(Note 8)
l
0 0.3 0.6 ns
Pipeline Latency Full Data Rate Mode
Double Data Rate Mode
6
6.5
Cycles
Cycles