Datasheet

LTC2142-14/
LTC2141-14/LTC2140-14
16
21421014fa
FUNCTIONAL BLOCK DIAGRAM
Figure 1. Functional Block Diagram
D1_0_1
–
/D1_0_1
+
to D1_12_13
–
/D1_12_13
+
(Pins 45/46,
47/48, 49/50, 51/52, 53/54, 55/56, 57/58): Channel 1
Double Data Rate Digital Outputs. Two data bits are mul-
tiplexed onto each differential output pair. The even data
bits (D0, D2, D4, D6, D8, D10, D12) appear when CLKOUT
+
is low. The odd data bits (D1, D3, D5, D7, D9, D11, D13)
appear when CLKOUT
+
is high.
OF2_1
–
/OF2_1
+
(Pins 59/60): Over/Underflow Digital
Output. OF2_1
+
is high when an overflow or underflow has
occurred. The over/underflow for both channels are mul-
tiplexed onto this pin. Channel 2 appears when CLKOUT
+
is low, and Channel 1 appears when CLKOUT
+
is high.
DIFF
REF
AMP
REF
BUF
2.2µF
0.1µF 0.1µF
INTERNAL CLOCK SIGNALSREFH REFL
CLOCK/DUTY
CYCLE
CONTROL
RANGE
SELECT
1.25V
REFERENCE
ENC
+
REFH REFL
ENC
–
CORRECTION
LOGIC
SDOCS
OGND
OF1
OV
DD
D1_13
CLKOUT
–
CLKOUT
+
D1_0
21421014 F01
SENSE
V
REF
CH 1
ANALOG
INPUT
2.2µF
V
CM1
0.1µF
V
DD
/2
OUTPUT
DRIVERS
MODE
CONTROL
REGISTERS
SCKPAR/SER SDI
t
t
t
GND
S/H
14-BIT
ADC CORE
CH 2
ANALOG
INPUT
S/H
14-BIT
ADC CORE
V
CM2
0.1µF
OF2
D2_13
D2_0
t
t
t
V
DD
PIN FUNCTIONS