Datasheet
7
21454314fa
LTC2145-14/
LTC2144-14/LTC2143-14
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 9)
SYMBOL PARAMETER CONDITIONS
LTC2145-14 LTC2144-14 LTC2143-14
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
CMOS Output Modes: Full Data Rate and Double Data Rate
V
DD
Analog Supply Voltage (Note 10)
l
1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
OV
DD
Output Supply Voltage (Note 10)
l
1.1 1.8 1.9 1.1 1.8 1.9 1.1 1.8 1.9 V
I
VDD
Analog Supply Current DC Input
Sine Wave Input
l
105.2
105.9
116 82.8
83.3
92 62.8
63.2
70 mA
mA
I
OVDD
Digital Supply Current Sine Wave Input, OV
DD
= 1.2V 8.5 7.1 5.4 mA
P
DISS
Power Dissipation DC Input
Sine Wave Input, OV
DD
= 1.2V
l
189
201
209 149
159
166 113
120
126 mW
mW
LVDS Output Mode
V
DD
Analog Supply Voltage (Note 10)
l
1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
OV
DD
Output Supply Voltage (Note 10)
l
1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
I
VDD
Analog Supply Current Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
107.3
108.7 123
84.7
86.1 97
64.6
66.1 75
mA
mA
I
OVDD
Digital Supply Current
(0V
DD
= 1.8V)
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
35.1
66.3 77
34.8
66 76
34.5
65.7 76
mA
mA
P
DISS
Power Dissipation Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
256
315 360
215
274 312
178
237 272
mW
mW
All Output Modes
P
SLEEP
Sleep Mode Power 1 1 1 mW
P
NAP
Nap Mode Power 16 16 16 mW
P
DIFFCLK
Power Increase with Differential Encode Mode Enabled
(No increase for Nap or Sleep Modes)
20 20 20 mW
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS
LTC2145-14 LTC2144-14 LTC2143-14
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
f
S
Sampling Frequency (Note 10)
l
1 125 1 105 1 80 MHz
t
L
ENC Low Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
3.8
2
4
4
500
500
4.52
2
4.76
4.76
500
500
5.93
2
6.25
6.25
500
500
ns
ns
t
H
ENC High Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
3.8
2
4
4
500
500
4.52
2
4.76
4.76
500
500
5.93
2
6.25
6.25
500
500
ns
ns
t
AP
Sample-and-Hold
Acquisition Delay Time
000ns
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)
t
D
ENC to Data Delay C
L
= 5pF (Note 8)
l
1.1 1.7 3.1 ns
t
C
ENC to CLKOUT Delay C
L
= 5pF (Note 8)
l
1 1.4 2.6 ns
t
SKEW
DATA to CLKOUT Skew t
D
– t
C
(Note 8)
l
0 0.3 0.6 ns
Pipeline Latency Full Data Rate Mode
Double Data Rate Mode
6
6.5
Cycles
Cycles