Datasheet

LTC2314-14
9
231414fa
For more information www.linear.com/LTC2314-14
TIMING DIAGRAMS
231414 TD04231414 TD03
231414 TD02231414 TD01
Hi-Z
SCK
OV
DD
/2
SDO
t
8
16TH EDGE
Hi-Z
CS
OV
DD
/2
SDO
t
9
V
OH
V
OL
SCK
OV
DD
/2
SDO
t
7
V
OH
V
OL
SCK
OV
DD
/2
SDO
t
4
Figure 1. SDO Into Hi-Z after 16TH SCK↓
Figure 3. SDO Data Valid Hold after SCK↓
Figure 2. SDO Into Hi-Z after CS↑
Figure 4. SDO Data Valid Access after SCK↓
BLOCK DIAGRAM
231414 BD
4
–
+
S/H
2.5V LDO
2×/4×
1.024V
BANDGAP
TIMING
LOGIC
1
6
7
8
THREE-STATE
SERIAL
OUTPUT
PORT
14-BIT SAR ADC
2
3
A
IN
REF
V
DD
OV
DD
2.2µF
GND
ANALOG
INPUT RANGE
0V TO V
REF
ANALOG SUPPLY
RANGE 2.7V TO 5.25V
DIGITAL SUPPLY
RANGE 1.71V TO 5.25V
5
2.2µF2.2µF
SDO
SCK
CS
TS8 PACKAGE
ALL CAPACITORS UNLESS
NOTED ARE HIGH QUALITY,
CERAMIC CHIP TYPE